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2021-04-06Merge tag 'mmc-2021-4-6' of https://source.denx.de/u-boot/custodians/u-boot-mmcWIP/06Apr2021Tom Rini4-12/+45
Update hwpartition usage Check bootbus's arguments workaround for erratum A-011334 for fsl_esdhc driver add pulse width detection workaround for fsl_esdhc driver Use alias num before checking mmc index when creating device
2021-04-06Merge https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini2-10/+7
- XHCI fixes
2021-04-06usb: xhci: Make debug output better readable and checkpatch cleanStefan Roese1-6/+3
This change makes debugging a bit easier as the output is better readable with the added space. The explicit le16_to_cpu() is not needed in the output. Also this patch moves the strings into one line to make the patch checkpatch clean. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de>
2021-04-06usb: xhci: Add missing xhci_readl()Aaron Williams1-4/+4
Accessing the xHCI controller registers should be done via the xhci_readl/writel functions. This patch adds this to a few missing places. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de>
2021-04-06Merge tag 'u-boot-amlogic-20210406' of ↵Tom Rini6-4/+545
https://source.denx.de/u-boot/custodians/u-boot-amlogic - Add MMIO MDIO mux driver - Add Amlogic G12A MDIO mux driver - Add DM_MDIO support for designware ethernet driver - Add Amlogic Meson8b and later designware ethernet glue driver - Switch all amlogic boards to Amlogic designware ethernet glue driver - Switch all amlogic boards to DM_MDIO when necessary - Remove all static ethernet setup code
2021-04-06Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini2-4/+37
- Enhance WDT handling (starting / stopping) and introduce CONFIG_WATCHDOG_AUTOSTART to allow disabling of autostart of the WDT (Pali)
2021-04-06Merge https://source.denx.de/u-boot/custodians/u-boot-cfi-flashTom Rini1-4/+33
- Fix detection of 8-bit bus flash devices via address shift
2021-04-06mmc: mmc-uclass: Use dev_seq() to read aliases node's indexAswath Govindraju1-7/+5
Use dev_seq() to read aliases node's index and pass it as device number for creating bulk device. Suggested-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-04-06mmc: Check for device with a seq number equal to num before checking against ↵Aswath Govindraju1-3/+5
index First check if there is an alias for the device tree node defined with the given num before checking against device index. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-04-06mmc: fsl_esdhc: add pulse width detection workaroundMichael Walle2-1/+8
HS400 mode on the LS1028A SoC isn't reliable. The linux driver has a workaroung for the pulse width detection. Apply this workaround in u-boot, too. This will make HS400 mode work reliably on the LS1028A SoC. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-04-06mmc: fsl_esdhc: add workaround for erratum A-011334Michael Walle2-1/+27
LS1028A SoCs are restricted in what divider values are allowed for HS400 mode. This is basically a port from the corresponding linux driver. Signed-off-by: Michael Walle <michael@walle.cc>
2021-04-06net: designware: remove amlogic compatiblesNeil Armstrong1-3/+0
These compatibles are now handled by the dwmac_meson8b glue driver. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-06net: designware: add Amlogic Meson8b & later glue driverNeil Armstrong3-0/+159
This adds a proper glue driver for the Designware DWMAC ethernet MAC IP found in the Amlogic Meson8, GXBB, GXL, GXM, G12A, G12B & SM1 SoCs. This is aimed to replace the static ethernet link setup found on the board init code for the Amlogic SoC based boards. Tested on a libretech-cc (S905x Internal RMII 10/100 PHY) and Khadas VIM3 (A113d with external 10/100/1000 RGMII PHY) to cover the most extreme setups. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-06net: add Amlogic Meson G12A MDIO MUX driverNeil Armstrong3-0/+157
The Amlogic G12A & compatible SoCs embeds a mux to either communicate with the external PHY or the internal 10/100 PHY. This adds support for this mux as a MDIO MUX device. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-04-06net: designware: add DM_MDIO supportNeil Armstrong1-1/+92
Add support for DM_MDIO to connect to PHY and expose a MDIO device for the internal MDIO bus in order to dynamically connect to MDIO PHYs with DT with eventual MDIO muxes in between. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-04-06net: add MMIO Register MDIO MUX driverNeil Armstrong3-0/+137
Add support for MMIO register MDIO muxes based on the Linux mdio-mux-mmioreg driver. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-04-06watchdog: Allow to use CONFIG_WDT without starting watchdogPali Rohár2-0/+18
In some cases it is useful to compile support for U-Boot command 'wdt' without starting HW watchdog in early U-Boot phase. For example when the user want to start the watchdog only on demand by some boot script. This change adds a new compile option WATCHDOG_AUTOSTART to control whether U-Boot should automatically start the watchdog during init phase or not. This option is enabled by default as it was the default behavior prior introducing this new change. When compiling U-Boot users can decide to turn this option off. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-06watchdog: Show error message when initr_watchdog() cannot start watchdogPali Rohár1-1/+7
Function wdt_start() may fail. So in initr_watchdog() function check return value of wdt_start() call and print error message when watchdog starting failed. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-06watchdog: Set/unset GD_FLG_WDT_READY flag in wdt_start()/wdt_stop()Pali Rohár1-3/+12
Watchdog is ready after successful call of ops->start() callback in wdt_start() function. And is stopped after successful call of ops->stop() callback in wdt_stop function. So move setting of GD_FLG_WDT_READY flag from initr_watchdog() function to wdt_start() and ensure that GD_FLG_WDT_READY flag is unset in wdt_stop() function. This change ensures that GD_FLG_WDT_READY flag is set only when watchdog is running. And ensures that flag is also also when watchdog was started not only by initr_watchdog() call (e.g. by U-Boot 'wdt' command). Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-06cfi_flash: Fix detection of 8-bit bus flash devices via address shiftJagannadha Sutradharudu Teki1-4/+33
We had a problem detecting 8/16bit flash devices connected only via 8bits to the SoC for quite a while. Commit 239cb9d9 [mtd: cfi_flash: Fix CFI flash driver for 8-bit bus support] finally fixed this 8-bit bus support. But also broke some other boards using this cfi driver. So this patch had to be reverted. I spotted a different, simpler approach for this 8-bit bus support on the barebox mailing list posted by Oleksij Rempel <bug-track@fisher-privat.net>: http://www.spinics.net/lists/u-boot-v2/msg14687.html Here the commit text: " Many cfi chips support 16 and 8 bit modes. Most important difference is use of so called "Q15/A-1" pin. In 16bit mode this pin is used for data IO. In 8bit mode, it is an address input which add one more least significant bit (LSB). In this case we should shift all adresses by one: For example 0xaa << 1 = 0x154 " This patch now is a port of this barebox patch to U-Boot. Along with the change w.r.t from barebox, Some flash chips can support multiple bus widths, override the interface width and limit it to the port width. Tested on 16-bit Spansion flash on sequoia. Tested 8-bit flashes like 256M29EW, 512M29EW. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Cc: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: Simon Glass <sjg@chromium.org> Cc: Mario Six <mario.six@gdsys.cc> Cc: York Sun <york.sun@nxp.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-04-06pinctrl: Return -ENOSYS when system call is not availableSimon Glass1-4/+6
Update the code to use -ENOSYS, which is the correct error code for an unimplemented system call in U-Boot. Also we should not check for a missing operations array as this is not permitted. For now this can be covered by an assert(). Signed-off-by: Simon Glass <sjg@chromium.org>
2021-04-06simple-pm-bus: Use -ENOSYS for checking missing system callSimon Glass1-2/+2
We don't need to check -ENOTSUPP since this is not used for this purpose in U-Boot. Update the code accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-04-06clk: Return -ENOSYS when system call is not availableSimon Glass1-4/+4
Update clk_composite_set_parent() to use -ENOSYS, which is the correct error code for U-Boot. Also rearrange the code so that the error condition is clearly indicated and the function runs to the end in the normal case, since this is the common style in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-04-06clk: Update drivers to use -EINVALSimon Glass9-17/+17
At present some drivers use -ENOSUPP to indicate that an unknown or unsupported clock is used. Most use -EINVAL, indicating an invalid value, so convert everything to that. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-06usb: Return -ENOSYS when system call is not availableSimon Glass1-1/+1
Update usb_gadget_release() to use -ENOSYS, which is the correct error code for U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-04-06dm: core: Use -ENOSPC in acpi_get_path()Simon Glass1-1/+1
Update this function to use -ENOSPC which is more commly used when a buffer runs out of space. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-31Merge tag 'xilinx-for-v2021.07' of ↵WIP/31Mar2021-nextTom Rini3-94/+190
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.07 net: - Fix gem PCS support spi: - Small trivial fixes zynq: - Enable time/timer commands - Update bitmain platform - Several DT changes zynqmp: - Update clock driver - mini config alignments - Add/update psu_init for zcu208/zcu216/zc1275 - Several DT changes - Enable efi debug command (also for Versal)
2021-03-30Merge tag 'u-boot-atmel-2021.07-a' of ↵WIP/30Mar2021-nextTom Rini1-3/+23
https://source.denx.de/u-boot/custodians/u-boot-atmel into next First set of u-boot-atmel features for 2021.07 cycle: This small feature set includes the implementation of the slew rate for the PIO4 pin controller device, and a fix for arm926ejs-based microprocessors that avoids a crash.
2021-03-30spi: xilinx_spi: Trivial fixes in axi qspi driverT Karthik Reddy1-5/+3
Use __func__ instead for function name in debug. Use Linux style u32 instead of uint32_t. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-03-30clk: zynqmp: Fix clk dump valuesT Karthik Reddy1-81/+170
With "clk dump" command, few clocks are showing up incorrect values and some clocks are displayed as "unknown". Add missing clocks to zynqmp clock driver to display proper clocks rates. Implement a simple way to get clock source, instead of calling functions. Change existing functions to this simple mechanism. Fix gem clock name "gem_rx" to "gem_tx" which was incorrect. Change dbf_fpd & dbf_lpd clk names to dbg_fpd & dbg_lpd. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
2021-03-30net: gem: Fix setting PCS auto-negotiation stateRobert Hancock1-8/+17
The code was trying to disable PCS auto-negotiation when a fixed-link node is present and enable it otherwise. However, the PCS registers were being written before the PCSSEL bit was set in the network configuration register, and it appears that in this state, PCS register writes are ignored. The result is that the intended change only took effect on the second network operation that was performed, since at that time PCSSEL is already enabled. Fix the order of register writes so that PCS registers are only written to after the PCS is enabled. Fixes: 26e62cc971 ("net: gem: Disable PCS autonegotiation in case of fixed-link") Signed-off-by: Robert Hancock <robert.hancock@calian.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-03-29Merge tag 'v2021.04-rc5' into nextWIP/29Mar2021-nextTom Rini7-19/+49
Prepare v2021.04-rc5
2021-03-27spi: spi-uclass: Add support to manually relocate spi memory opsT Karthik Reddy1-0/+11
Add spi memory operations to relocate manually when CONFIG_NEEDS_MANUAL_RELOC is enabled. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
2021-03-27cpu: Rename SPL_CPU_SUPPORT to SPL_CPUSimon Glass2-6/+2
The _SUPPORT suffix is from an earlier time and interferes with use of the CONFIG_IS_ENABLED() macro. Rename the option to drop the suffix. Tidy up the TODO that prompted this. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27sf: Support querying write-protectSimon Glass5-0/+38
This feature was dropped from U-Boot some time ago: f12f96cfaf5 (sf: Drop spl_flash_get_sw_write_prot") However, we do need a way to see if a flash device is write-protected, since if it is, it may not be possible to write to do (i.e. failing to write is expected). I am not sure of the correct layer to implement this, so this patch is a stab at it. If spi-flash makes sense then I will add to the 'sf' also. Re the points mentioned in the removal commit: 1) This kind of requirement can be achieved using existing flash operations and flash locking API calls instead of making a separate flash API. Which uclass is this? 2) Technically there is no real hardware user for this API to use in the source tree. I do want coral (at least) to support this. 3) Having a flash operations API for simple register read bits also make difficult to extend the flash operations. This new patch only mentions write-protect being on or off, rather than the actual mechanism. 4) Instead of touching generic code, it is possible to have this functionality inside spinor operations in the form of flash hooks or fixups for associated flash chips. That sounds to me like what drivers are for. But we still need some sort of API for it to be accessible. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27sandbox: Provide a way to bind fixed/removeable devicesSimon Glass1-4/+4
At present when a file is bound to a host device it is always marked as removeable. Arguably the device is removeable, since it can be unbound at will. However while it is bound, it is not considered removable by the user. Also it is useful to be able to model both fixed and removeable devices for code that distinguishes them. Add a -r flag to the 'host bind' command and plumb it through to provide this feature. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27sandbox: cros_ec: Only write EC state when the EC is probedSimon Glass1-0/+4
This can crash if the EC has not yet been probed. Add a check to prevent this. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27sandbox: Only call timer_timebase_fallback() if presentSimon Glass1-1/+2
This function only exists if CPU is enabled. Update the code to take account of this, so that it does not have to be enabled on all sandbox builds. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-03-27x86: video: Allow coreboot video to be used on any x86 boardSimon Glass2-5/+13
When booting from coreboot we need this driver for the video to work. Update the driver to be usable on any board. The driver disables itself if it sees that is not booted from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27video: Fix video on coreboot with the copy bufferSimon Glass1-5/+2
The copy buffer, if enabled, prevents booting from coreboot correctly, since no memory is allocated for it. Allow it to fall back to disabled in this situation. This ensures that a console is displayed, even if it is slow. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: Make coreboot sysinfo available to any x86 boardSimon Glass3-3/+3
It is possible to boot U-Boot for chromebook_coral either 'bare metal' or from coreboot. In the latter case we want to provide access to the coreboot sysinfo tables. Move the definitions into a file available to any x86 board. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27mmc: pci_mmc: Set up the card detectSimon Glass1-1/+5
The driver currently reads the card-detect but does not register it with the MMC stack. Update this so that card-detect works as expected. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27tegra: i2c: Drop LOG_DEBUGSimon Glass1-1/+0
We should not enable debugging by default. Drop this. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: Probe device if needed in intel_gpio_xlate()Simon Glass1-1/+13
The Intel GPIO binding allows GPIOs to be globally numbered, so that it does not matter which GPIO bank is specified in the device tree. This is convenient and avoid confusion since the banks do not have the same number of GPIOs and the numbering is not sequential. The GPIO uclass ensures that the device mentioned in the devicetree binding is probed. It is fine for the driver to update gpio_desc to point to a different driver, but this may not have been probed. If it has not been, then it cannot be claimed since there is no uclass data. We could handle this in the GPIO uclass but so far it is an unusual situation so it is probably not worth the extra code. Handle this case in the GPIO driver by probing the selected device if necessary. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: p2sb: Drop LOG_DEBUGSimon Glass1-1/+0
We should not enable debugging by default. Drop this. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27mtd: spi_flash_free()Heinrich Schuchardt1-5/+0
dfu_free_entities() invoking dfu_free_entity_sf() has let to segementation faults due to double freeing the same device. spi_flash_free() is not relevant for the driver model but exists only for compatibility with old drivers. We must not remove any device here: * The device may still be referenced. * We don't want to have to probe again. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-03-26Merge tag 'dm-pull-26mar21-take2' of git://git.denx.de/u-boot-dm into nextWIP/26Mar2021-nextTom Rini17-125/+237
dtoc support for of-platdata-inst driver model support for of-platdata-inst support of-platdata-inst on x86 / coral binman support for exapanded entries binman convert docs to reST ti-sysc fix for duplicate uclass driver patman minor improvements pylibfdt build only if needed correct obscure CI error with OF_PLATDATA_INST
2021-03-26dm: core: Use separate priv/plat data regionSimon Glass2-6/+15
Make use of the new priv/plat data region if enabled. This is implemented as a simple offset from the position set up by dtoc to the new position. So long as all access goes through dm_priv_to_rw() this is safe. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26dm: core: Allow storing priv/plat data separatelySimon Glass1-0/+12
At present the device priv/data data allocated by dtoc is stored in the data section along with other variables. On some platforms it is better to allocate space for it separately, e.g. if SPL is running from read-only memory. Create a new space with the same size as that allocated by dtoc, ready for use. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26dm: core: Move flags to device-runtime infoSimon Glass1-0/+33
When of-platdata-inst is active, use the flags in the new udevice_rt table, dropping them from the main struct udevice. This ensures that the latter is not updated at runtime. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-07-13 05:30:34 +0000