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2017-12-07i2c: meson: add some commentsBeniamino Galvani1-6/+19
Add some comment describing the purpose of struct members and functions. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2017-12-07i2c: meson: fix return codes on errorBeniamino Galvani1-2/+2
Change meson_i2c_xfer_msg() to return -EREMOTEIO in case of NACK, as done by other drivers. Also, don't change the return error in meson_i2c_xfer(). Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2017-12-07i2c: meson: reduce timeoutBeniamino Galvani1-1/+1
The datasheet doesn't specify a suggested timeout and 500ms seems very long: reduce it to 100ms. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2017-12-07i2c: meson: improve Kconfig descriptionBeniamino Galvani1-1/+6
Expand the Kconfig description with hardware features. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2017-12-07sunxi: Fix A20-OLinuXino-MICRO LAN8710 supportStefan Mavrodiev1-0/+8
>From revision J the board uses new phy chip LAN8710. Compared with RTL8201, RA17 pin is TXERR. It has pullup which causes phy not to work. To fix this PA17 is muxed with GMAC function. This makes the pin output-low. Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-12-06driver: fsl-mc: MC object cleanup when DPL not loadedYogesh Gaur1-1/+2
For case when MC is loaded but DPL is not deployed perform MC object [DPBP, DPIO, DPNI and DPRC] cleanup. Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-12-06driver: net: fsl-mc: flib changes for MC 10.3.0Yogesh Gaur9-483/+532
Existing MC driver framework is based on MC-9.x.x flib. This patch migrates MC obj (DPBP, DPNI, DPRC, DPMAC etc) to use latest MC flib which is MC-10.3.0. Changes introduced due to migration: 1. To get OBJ token, pair of create and open API replaces create APIs 2. Pair of close and destroy APIs replaces destroy APIs 3. For version read, get_version APIs replaces get_attributes APIs 4. dpni_get/reset_statistics APIs replaces dpni_get/set_counter APIs 5. Simplifies struct dpni_cfg and removes dpni_extended_cfg struct 6. Single API dpni_get_buffer_layout/set_buffer_layout replaces dpni_get_rx/set_rx, tx related, tx_conf_buffer_layout related APIs. New API takes a queue type as an argument. 7. Similarly dpni_get_queue/set_queue replaces dpni_get_rx_flow/set_rx_flow , tx_flow related, tx_conf related APIs Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-12-04Merge git://git.denx.de/u-boot-uniphierTom Rini18-48/+22
2017-12-04Merge git://git.denx.de/u-boot-cfi-flashTom Rini1-3/+9
2017-12-04drivers: firmware: psci: use pr_* log functions instead of printf()Masahiro Yamada1-3/+4
In Linux, the warning messages are printed out by pr_warn(). We can use Linux-like log functions in tree-wide. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-12-04mtd: nand: denali: consolidate include directivesMasahiro Yamada1-3/+3
Include necessary headers explicitly without relying on indirect header inclusion. <common.h>, <malloc.h> are unneeded. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-04mtd: nand: denali_dt: replace printf() with pr_err()Masahiro Yamada1-2/+2
The Linux derived log functions can be used anywhere and easily turned on/off by CONFIG_LOGLEVEL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-04mtd: nand: Rename nand.h into rawnand.hMasahiro Yamada16-16/+16
This header was renamed to rawnand.h in Linux. The following is the corresponding commit in Linux. commit d4092d76a4a4e57b65910899948a83cc8646c5a5 Author: Boris Brezillon <boris.brezillon@free-electrons.com> Date: Fri Aug 4 17:29:10 2017 +0200 mtd: nand: Rename nand.h into rawnand.h We are planning to share more code between different NAND based devices (SPI NAND, OneNAND and raw NANDs), but before doing that we need to move the existing include/linux/mtd/nand.h file into include/linux/mtd/rawnand.h so we can later create a nand.h header containing all common structure and function prototypes. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-04mtd: nand: denali: remove ad-hoc board_nand_init() entryMasahiro Yamada1-26/+0
This driver is highly dependent on the configuration from denali_dt.c Please enable CONFIG_NAND_DENALI_DT if you use this driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-04mtd: nand: denali: remove bogus __maybe_unusedMasahiro Yamada1-1/+1
denali_setup_data_interface() is always used. I put __maybe_unused for a temporal use, then forgot to delete it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-04mtd: cfi: Fix checking status register featureYork Sun1-3/+9
Commit 72443c7f7d21 ("mtd: cfi: Add support for status register polling") added a feature check to determine if status register is available for certain flash chips. The "lower software bits" register used to determine this feature is not backward compati- ble. Older flash chips without this feature has reserved value 0xff. Instead of checking "lower software bits" register, use CFI primary vendor-specific extended query. Since CFI version 1.4, software features can be read from offset 0x53 according to document AN201168 from Cypress. Signed-off-by: York Sun <york.sun@nxp.com> CC: Marek Vasut <marek.vasut@gmail.com> Tested-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-12-02sunxi: video: HDMI: split VSYNC and HSYNC polarity settingsVasily Khoruzhick1-9/+5
These are actually different bits, and since some monitors (Benq BL2420PT) have modes with different HSYNC and VSYNC polarity, we should set them independently Tested on Pine64-LTS with Benq BL2420PT monitor. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-12-02video: sunxi: de2: add support for LCD SimpleFBIcenowy Zheng1-1/+10
Add support for setting up SimpleFB for LCD display output in DE2 SimpleFB setup code. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-11-30rockchip: rk3128: add sdram driverKever Yang2-0/+60
RK3128 support up to 2GB DDR3 sdram, one channel, 32bit data width. This patch is only used for U-Boot, but not for SPL which will comes later, maybe after we merge all the common code into a common file. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: rk3128: add pinctrl driverKever Yang3-2/+199
Add rk3128 pinctrl driver and grf/iomux structure definition. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: rk3128: add clock driverKever Yang2-1/+598
Add rk3128 clock driver and cru structure definition. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-shTom Rini9-6/+423
2017-11-30Merge git://git.denx.de/u-boot-marvellTom Rini1-0/+2
2017-11-30fix: nand: pxa3xx: fix defined but not used warningsSean Nyekjaer1-0/+2
bbt_mirror_descr and bbt_main_descr is defined but not used when compiling without CONFIG_SYS_NAND_USE_FLASH_BBT set. Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Signed-off-by: Stefan Roese <sr@denx.de>
2017-11-29mmc: atmel_sdhci: not on capabilities to set gck rateLudovic Desroches1-10/+2
The capabilities have default values which doesn't reflect the reality when it concerns the base clock and the mul value. Use a fixe rate for the gck. 240 MHz is an arbitrary choice, it is a multiple of the maximum SD clock frequency handle by the controller and it allows to get a 400 kHz clock for the card initialisation. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-11-29clk: at91: clk-generated: fix incorrect index of clk sourceWenyou Yang1-6/+8
Differentiate the generic clock source selection value from the parent clock index to fix the incorrect assignment of the generic clock source selection. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-11-29clk: at91: clk-generated: select absolute closest rateLudovic Desroches1-3/+1
To get the same behavior as the Linux driver, instead of selecting the closest inferior rate, select the closest inferior or superior rate Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-11-29clk: at91: Kconfig: fix the dependency of AT91_UTMIWenyou Yang1-3/+3
What the AT91_UTMI depends on SPL_DM isn't right. AT91_UTMI is not only used in SPL, also in other place, even if SPL_DM isn't enabled. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-11-29clk: clk_stm32fx: add clock configuration for mmc usagePatrice Chotard1-1/+100
MMC block needs 48Mhz source clock, for that we choose to select the SAI PLL. Update also stm32_clock_get_rate() to retrieve the MMC clock source needed in MMC driver. STM32F4 uses a different RCC variant than STM32F7. For STM32F4 sdmmc clocks bit are located into dckcfgr register whereas there are located into dckcfgr2 registers on STM32F7. In both registers, bits CK48MSEL and SDMMC1SEL are located at the same position. Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29dm: misc: bind STM32F4/F7 clock from rcc MFD driverPatrice Chotard2-46/+50
Like STM32H7, now STM32F4/F7 clock drivers are binded by MFD stm32_rcc driver. This also allows to add reset support to STM32F4/F7 SoCs family. As Reset driver is not part of SPL supported drivers, don't bind it in case of SPL to avoid that stm32_rcc_bind() returns an error. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29clk: stm32fx: migrate define from rcc.h to driverPatrice Chotard1-1/+18
STM32F4 doesn't get rcc.h file, to avoid compilation issue, migrate RCC related defines from rcc.h to driver file and remove rcc.h file. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29clk: stm32f7: rename clk_stm32f7.c to clk_stm32f.cPatrice Chotard3-9/+13
Now that clk_stm32f7.c manages clocks for both STM32F4 and F7 SoCs rename it to a more generic clk_stm32f.c Fix also some checkpatch errors/warnings. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29clk: stm32f7: add STM32F4 supportPatrice Chotard1-43/+66
STM32F4 and STM32F7 RCC clock IP are very similar. Same driver can be used to managed RCC clock for these 2 SoCs. Differences between STM32F4 and F7 will be managed using different compatible string : _ overdrive clock is only supported by STM32F7 _ different sys_pll_psc parameters can be used between STM32F4 and STM32F7. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29clk: stm32f7: add dedicated STM32F7 compatible stringPatrice Chotard1-0/+1
Add a dedicated stm32f7 compatible string to use clk_stm32f7 driver with both STM32F4 and STM32F7 SoCs. It will be needed to manage differences between these 2 SoCs. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29clk: stm32f7: retrieve PWR base address from DTPatrice Chotard1-11/+21
PWR IP is used to enable over-drive feature in order to reach a higher frequency. Get its base address from DT instead of hard-coded value Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-30nds32: ftsdc010: Fix SD detech fail on AE3XX.Rick Chen1-1/+0
AE3XX can not support SD high-speed mode. SW can work-around by removing HS capibility. Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-30nds32: ftsdc010: fix wait status error coding.Rick Chen1-2/+3
Bit of DATA_END and DATA_CRC_OK shall be checked for returning pass or fail of a request. Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-30nds32: ftsdc010: Support ftsdc010 DM.Rick Chen2-31/+161
ftsdc010 support device tree flow. Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-30nds32: mmc: Support ftsdc010 DM.Rick Chen3-0/+149
Add nds32_mmc to support ftsdc010 dm flow. Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-30cosmetic: atcspi200: Rename function name as atcspi200Rick Chen1-48/+48
Integrate function and struct name from ae3xx to atcspi200 will be more reasonable. Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-30spi: nds_ae3xx: Rename nds_ae3xx_spi as atcspi200_spiRick Chen3-6/+6
atcspi200 is Andestech spi ip which is embedded in AE3XX and AE250 platforms. So rename as atcspi200 will be more reasonable to be used in different platforms. Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-30atcpit100: timer: Remove arch dependency.Rick Chen1-1/+1
ATCPIT100 is often used in AE3XX platform which is based on NDS32 architecture recently. But in the future Andestech will have AE250 platform which is embeded ATCPIT100 timer based on RISCV architecture. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-30cosmetic: atcpit100_timer: Use device api to get platdataRick Chen1-2/+2
Use dev_get_platdata to get private platdata. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-30cosmetic: atcpit100_timer: Rename function name as atcpit100Rick Chen1-17/+17
Integrate function and struct name as atcpit100 will be more reasonable. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-30ae3xx: timer: Rename AE3XX to ATCPIT100Rick Chen3-4/+5
ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-30ae3xx: timer: Fix ae3xx timer work abnormal in 64 bit.Rick Chen1-2/+2
It will be work fine with unsigned long declaretion in timer register struct when system is 32 bit. But it will not work well when system is 64 bit. Replace it by u32 and verify both ok in 32/64 bit. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-30gpio: rmobile: Set GPIO mode in GPSR when requestedMarek Vasut1-1/+19
When requesting a GPIO, set the PFC GPSR register to GPIO mode, otherwise the GPIO cannot work. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30pfc: rmobile: Add hook to configure pin as GPIOMarek Vasut2-0/+30
Add hook into the PFC driver to allow the GPIO driver to toggle GPSR registers into GPIO mode when GPIO is requested. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30pinctrl: rmobile: Add support for setting single pinsMarek Vasut1-0/+31
Add code to handle single pins nodes from DT in addition to already support groups handling. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30net: ravb: Fix reset GPIO handlingMarek Vasut1-3/+4
Fix handling of the reset GPIO. Drop the _nodev() suffix from the gpio_request_by_name() call as there is now a proper DM capable GPIO driver. Also check if the GPIO is valid before freeing it in remove path, otherwise U-Boot will crash. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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