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2022-12-05spi: cadence-qspi: Remove condition for calling enable linear modeAshok Reddy Soma1-5/+1
cadence_qspi_apb_enable_linear_mode() has a weak function defined, so no need to gaurd this under if (CONFIG_IS_ENABLED(ARCH_VERSAL)). In cadence_qspi_apb_write_execute(), enable linear mode is called twice by mistake, remove extra one. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20221129114134.18909-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05spi: zynqmp_qspi: Add support for 64-bit read/writeVenkatesh Yadav Abbarapu1-2/+4
When we pass the 64-bit address to read/write, only lower 32-bit address is getting updated. Program the upper 32-bit address in the DMA destination memory address MSBs register, which can handle upto 44-bit destination address. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20221125104413.26140-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05spi: zynqmp_gqspi: Update tapdelay valueT Karthik Reddy1-1/+1
The driver was using an incorrect value for GQSPI_LPBK_DLY_ADJ_DLY_1 tapdelay for Versal for frequencies above 100MHz. Change it from 2 to 1 based on the recommended value in IP spec. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20221123090451.11409-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05net: xilinx_axi: check PCS/PMA PHY status in setup_phyAndy Chiu1-0/+44
Both PCS/PMA PHY and the external PHY need to have a valid link status in order to have Ethernet traffic. Check and wait this status at setup_phy() so that we could diagnose if there is a PHY issue. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Reviewed-by: Greentime Hu <greentime.hu@sifive.com> Link: https://lore.kernel.org/r/20221101035800.912644-3-andy.chiu@sifive.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05net: xilinx_axi: add PCS/PMA PHYAndy Chiu1-2/+24
If we bridge an external PHY to Xilinx's PCS/PMA PHY and would like to get and set the real status of the PHY facing the external world. Then we should phy_connect() to the external PHY instead of the PCS/PMA one. Thus, we add a pcs-handle DT entry, which have been merged in Linux, and leave the configuration of it to the driver itself. Unlike Linux, where the PCS/PMA PHY is managed by phylink, managing the PCS/PMA PHY is only internal to the driver in U-Boot. The PCS/PMA PHY pressents only when the phy-mode is configured as SGMII or 1000Base-X, so it is always 1 Gbps and full-duplex and we may skip passing link information out. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Reviewed-by: Greentime Hu <greentime.hu@sifive.com> Link: https://lore.kernel.org/r/20221101035800.912644-2-andy.chiu@sifive.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-02bus: Optionally include TI sysc driver in SPL/TPLPaul Barker3-2/+12
The TI sysc bus driver is required to allow access to the SPI bus on am335x platforms. To support SPI boot this driver needs to be enabled in the SPL/TPL as appropriate. Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2022-12-02bus: TI sysc driver requires DMPaul Barker1-1/+1
This driver does not build if CONFIG_DM is disabled as it uses the function `dev_get_priv`. Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2022-12-02dm: core: Fix iteration over driver_info recordsPaul Barker1-3/+3
We should only perform additional iteration steps when needed to initialize the parent of a device. Other binding errors (such as a missing driver) should not lead to additional iteration steps. Unnecessary iteration steps can cause issues when memory is tightly constrained (such as in the TPL/SPL) since device_bind_by_name() unconditionally allocates memory for a struct udevice. On the SanCloud BBE this led to boot failure caused by memory exhaustion in the SPL when booting from SPI flash. Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2022-11-28phy: add driver for Intel XWAY PHYTim Harvey4-0/+57
Add a driver for the Intel XWAY GbE PHY: - configure RGMII using dt phy-mode and standard delay properties - use genphy_config Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-11-28net: macb: Fix race caused by flushing unwanted descriptorsYaron Micher1-12/+39
The rx descriptor list is in cached memory, and there may be multiple descriptors per cache-line. After reclaim_rx_buffers marks a descriptor as unused it does a cache flush, which causes the entire cache-line to be written to memory, which may override other descriptors in the same cache-line that the controller may have written to. The fix skips freeing descriptors that are not the last in a cache-line, and if the freed descriptor is the last one in a cache-line, it marks all the descriptors in the cache-line as unused. This is similarly to what is done in drivers/net/fec_mxc.c In my case this bug caused tftpboot to fail some times when other packets are sent to u-boot in addition to the ongoing tftp (e.g. ping). The driver would stop receiving new packets because it is waiting on a descriptor that is marked unused, when in reality the descriptor contains a new unprocessed packet but while freeing the previous buffer descriptor & flushing the cache, the driver accidentally marked the descriptor as unused. Signed-off-by: Yaron Micher <yaronm@hailo.ai>
2022-11-28drivers: net: aquantia: fix typosTim Harvey1-4/+4
Fix a couple of typos: - s/Acquantia/Aquantia/ - s/firmare/firmware/ Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-28net: dwc_eth_qos: Add support for bulk RX descriptor cleaningMarek Vasut2-23/+46
Add new desc_per_cacheline property which lets a platform run RX descriptor cleanup after every power-of-2 - 1 received packets instead of every packet. This is useful on platforms where (axi_bus_width EQOS_AXI_WIDTH_n * DMA DSL inter-descriptor word skip count + DMA descriptor size) is less than cache line size, which necessitates packing multiple DMA descriptors into single cache line. In case of TX descriptors, this is not a problem, since the driver always does synchronous TX, i.e. the TX descriptor is always written, flushed and polled for completion in eqos_send(). In case of RX descriptors, it is necessary to update their status in bulk, i.e. after the entire cache line worth of RX descriptors has been used up to receive data. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-28net: dwc_eth_qos: Split TX and RX DMA ringsMarek Vasut2-12/+24
Separate TX and RX DMA rings to make their handling slightly clearer. This is a preparatory patch for bulk RX descriptor flushing. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-28liteeth: LiteX Ethernet deviceJoel Stanley3-0/+220
LiteX is a soft system-on-chip that targets FPGAs. LiteETH is a basic network device that is commonly used in LiteX designs. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-27usb: dwc3: Drop support for "snps, ref-clock-period-ns" DT propertyMarek Vasut1-4/+0
Drop support for quickly deprecated DT property "snps,ref-clock-period-ns" to prevent its proliferation. Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de>
2022-11-27usb: dwc3: Program GFLADJSean Anderson2-0/+44
GUCTL.REFCLKPER can only account for clock frequencies with integer periods. To address this, program REFCLK_FLADJ with the relative error caused by period truncation. The formula given in the register reference has been rearranged to allow calculation based on rate (instead of period), and to allow for fixed-point arithmetic. Additionally, calculate a value for 240MHZDECR. This configures a simulated 240Mhz clock using a counter with one fractional bit (PLS1). This register is programmed only for versions >= 2.50a, since this is the check also used by commit db2be4e9e30c ("usb: dwc3: Add frame length adjustment quirk"). [ marek: Ported from Linux kernel commit 596c87856e08d ("usb: dwc3: Program GFLADJ") ] Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux
2022-11-27usb: dwc3: Calculate REFCLKPER based on reference clockSean Anderson1-2/+13
Instead of using a special property to determine the reference clock period, use the rate of the reference clock. When we have a legacy snps,ref-clock-period-ns property and no reference clock, use it instead. Fractional clocks are not currently supported, and will be dealt with in the next commit. [ marek: Ported from Linux kernel commit 5114c3ee24875 ("usb: dwc3: Calculate REFCLKPER based on reference clock") ] Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux
2022-11-27usb: dwc3: reference clock period configurationBalaji Prakash J2-0/+33
Set reference clock period when it differs from dwc3 default hardware set. We could calculate clock period based on reference clock frequency. But this information is not always available. This is the case of PCI bus attached USB host. For that reason we use a custom property. Tested (USB2 only) on IPQ6010 SoC based board with 24 MHz reference clock while hardware default is 19.2 MHz. [ baruch: rewrite commit message; drop GFLADJ code; remove 'quirk-' from property name; mention tested hardware ] [ marek: Ported from Linux kernel commit 7bee318838890 ("usb: dwc3: reference clock period configuration") ] Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux
2022-11-27usb: dwc3: Cache ref_clk pointer in struct dwc3Marek Vasut2-0/+12
Cache ref_clk clock pointer in struct dwc3 . This is a preparatory patch for subsequent backports from Linux kernel which configure GFLADJ register content based on the ref_clk rate and therefore need access to the ref_clk pointer. It is possible to extract the clock pointer from existing clk_bulk list of already claimed clock, no need to call clk_get*() again. Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de>
2022-11-27usb: Expand buffer size in usb_find_and_bind_driver()Marek Vasut1-1/+1
The "generic_bus_%x_dev_%x" string which is printed into this buffer can be up to 34 characters long ("generic_bus_12345678_dev_12345678"). The buffer would be clipped by snprintf() if both %x were at maximum range. Make sure the buffer is long enough to cover such possibility. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-24ram: ast2600: Align the RL and WL settingDylan Hung1-0/+9
Use macro to represent the RL and WL setting to ensure the PHY and controller setting are aligned. Review-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-11-24ram: ast2600: Improve ddr4 timing and signal qualityDylan Hung1-25/+138
Adjust the following settings to get better timing and signal quality. 1. write DQS/DQ delay - 1e6e2304[0] - 1e6e2304[15:8] 2. read DQS/DQ delay - 0x1e6e0298[0] - 0x1e6e0298[15:8] 3. CLK/CA timing - 0x1e6e01a8[31] 4. Read and write termination - change RTT_ROM from 40 ohm to 48 ohm (MR1[10:8]) - change RTT_PARK from disable to 48 ohm (MR5[8:6]) - change RTT_WR from 120 ohm to disable (MR2[11:9]) - change PHY ODT from 40 ohm to 80 ohm (0x1e6e0130[10:8]) Note1: Both DDR-PHY and DDR controller have their own registers for DDR4 Mode Registers (MR0~MR6). This patch introduces macros to synchronize the MR value on both sides. Note2: the waveform meansurement can be found in item #21 of Aspeed AST26x0 Application note (AP note). Review-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-11-24ram: ast2600: Fix incorrect statement of the register pollingDylan Hung1-6/+1
The condition "~data" in the if-statement is a typo. The original intention is to poll if SDRAM_PHYCTRL0_INIT bit equals to 0. So use "data == 0" for instead. Besides, the bit[1] of "phy_status" register is hardwired to SDRAM_PHYCTRL0_INIT (with inverse logic). Since SDRAM_PHYCTRL0_INIT has already done, remove the unnecessary checking of phy_status[1]. Fixes: fde93143469f ("ram: aspeed: Add AST2600 DRAM control support") Review-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-11-23Merge tag 'u-boot-amlogic-20221122' of ↵WIP/23Nov2022Tom Rini1-0/+70
https://source.denx.de/u-boot/custodians/u-boot-amlogic - Implement setbrg op to meson serial device - Re-add the old PHY reset binding for nanopi-k2
2022-11-22sandbox: check lseek return value in handle_ufi_commandHeinrich Schuchardt1-3/+7
Invoking lseek() may result in an error. Handle it. Addresses-Coverity-ID: 376212 ("Error handling issues (CHECKED_RETURN)") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-11-22arm: amlogic: add setbrg op to serial deviceEdoardo Tomelleri1-0/+70
Implement setbrg in amlogic/meson serial device with driver model similar to how the meson_uart.c driver does it in Linux. Also configure (probe) the serial device with the new reg5 register. Signed-off-by: Edoardo Tomelleri <e.tomell@gmail.com> Link: https://lore.kernel.org/r/20220918161701.572814-1-e.tomell@gmail.com Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2022-11-22Merge tag 'xilinx-for-v2023.01-rc3' of ↵Tom Rini10-32/+109
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2023.01-rc3 microblaze: - Enable 32 bit addressing mode for SPIs zynq: - Minor DT fixes (PL clock enabling) zynqmp: - Disable watchdog by default - Remove unused xlnx,eeprom chosen support - Add missing symlink for vck190 SC revB - Use mdio bus with ethernet-phy-id description versal: - Add mini qspi/ospi configuration versal-net: - Add soc driver - Fix Kconfig entry for SOC - Fix loading address location for MINI configuration - Disable LMB for mini configuration net: - Fix ethernet-phy-id usage in the code pinctrl: - Revert high impedance/output enable support timer: - Fix timer relocation for Microblaze - Fix timer wrap in 32bit Xilinx timer driver
2022-11-22spi: cadence-qspi: Fix compilation error in mini u-boot flash resetAshok Reddy Soma1-2/+2
When cadence_qspi_versal_flash_reset() function is called in mini u-boot where there is no firmware support, it is missing defines for macro's BOOT_MODE_POR_0 & BOOT_MODE_POR_1. Remove them and replace with already define macro's which have same values as these. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20221116141155.14788-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22qspi: versal-net: Add condition for tapdelay registerAshok Reddy Soma1-1/+2
Add CONFIG_ARCH_VERSAL_NET to select tapdelay register for versal-net. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/2500dd688214e2ec2d54ed3fabbfee0b1ca861a6.1668613229.git.michal.simek@amd.com
2022-11-22soc: xilinx: versal-net: Add soc_xilinx_versal_net driverMichal Simek3-0/+87
Add soc_xilinx_versal_net driver to identify the family & revision of versal-net SoC. Add Kconfig option CONFIG_SOC_XILINX_VERSAL_NET to enable/disable this driver. To enable this driver by default, add this config to xilinx_versal_net_virt_defconfig file. This driver will be probed using platdata U_BOOT_DEVICE structure which is specified in mach-versal-net/cpu.c. Signed-off-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/613d6bcffd9070f62cf348079ed16c120f8fc56f.1668612993.git.michal.simek@amd.com
2022-11-22net: phy: Fix ethernet-phy-id <dot> in the codeMichal Simek1-2/+2
Use dot instead of comma. The fix doesn't affect anything but it is good to be aligned with used pattern. The first is used only for string size calculation and the second change is in the comment. Fixes: db681d4929ca ("net: phy: Add new read ethernet phy id function") Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22timer: xilinx-timer: use timer_conv_64() to fix timer wrap aroundOvidiu Panait1-1/+1
Current xilinx_timer_get_count() implementation does not take into account the periodic 32-bit wrap arounds, as it directly returns the 32-bit counter register value. The roll-overs cause problems in the upper timer layers, as generic timer code expects an incrementing 64-bit value from get_count() to work correctly. Add the missing 64-bit up-conversion to fix random hangs/delays in __udelay(). Fixes: a36d86720f ("microblaze: Convert axi timer to DM driver") Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Reviewed-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221012053656.1492457-3-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22timer-uclass: relocate ops pointers for CONFIG_NEEDS_MANUAL_RELOCOvidiu Panait1-0/+14
Relocate timer_ops pointers when CONFIG_NEEDS_MANUAL_RELOC is enabled. The (gd->flags & GD_FLG_RELOC) check was added to make sure the reloc_done logic works for drivers that use DM_FLAG_PRE_RELOC. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20221012053656.1492457-2-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22timer-uclass: add timer_get_ops() macroOvidiu Panait1-1/+1
Align timer uclass with the other subsystems and provide a timer_get_ops() convenience macro. Using this instead of the generic device_get_ops() also prevents -Wdiscarded-qualifiers warnings when used with non-const variables. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20221012053656.1492457-1-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22xilinx: common: Remove zynq_board_read_rom_ethaddr()Venkatesh Yadav Abbarapu1-16/+0
Removing the zynq_board_read_rom_ethaddr() function as xlnx,eeprom is not used anymore. As all board dts to use nvmem alias instead of xlnx,eeprom. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20221017094818.17996-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22Revert "pinctrl: zynqmp: Add support for output-enable and bias-high-impedance"Michal Simek1-9/+0
This reverts commit 123462e5e534d6e17b1b7d2006734bbe54b03e0a. On systems with older PMUFW using these pinctrl properties can cause system hang because there is missing feature autodetection. When it is implemented support for these two properties should go back. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c2900319ea80484f21692997f296269aee701c1f.1665659138.git.michal.simek@amd.com
2022-11-22watchdog: Drop GD_FLG_WDT_READY as it's not used any moreStefan Roese1-1/+0
Since commit c2fd0ca1a822 ("watchdog: Integrate watchdog triggering into the cyclic framework") GD_FLG_WDT_READY has become write-only. This patch now removes this flag completely. The vacant spot in gd_flags is filled with the newly introduced GD_FLG_CYCLIC_RUNNING flag. Suggested-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by: Stefan Roese <sr@denx.de>
2022-11-22watchdog: designware: make reset really optionalQuentin Schulz1-4/+5
Checking for DM_RESET is not enough since not all watchdog implementations use a reset lane. Such is the case for Rockchip implementation for example. Since reset_assert_bulk will only succeed if the resets property exists in the watchdog DT node, it needs to be called only if a reset property is present. This adds a condition on the resets property presence in the watchdog DT node before assuming a reset lane needs to be fetched with reset_assert_bulk, by calling ofnode_read_prop. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2022-11-21usb: gadget: dfu: Fix the unchecked length fieldVenkatesh Yadav Abbarapu1-21/+37
DFU implementation does not bound the length field in USB DFU download setup packets, and it does not verify that the transfer direction. Fixing the length and transfer direction. CVE-2022-2347 Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Reviewed-by: Marek Vasut <marex@denx.de>
2022-11-15clk: microchip: mpfs: fix criticality of peripheral clocksConor Dooley1-7/+21
Sync the critical clocks in the U-Boot driver with those marked as critical in Linux. The Linux driver has an explanation of why each clock is considered to be critical, so import that too. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
2022-11-15clk: microchip: mpfs: fix periph clk parentageConor Dooley3-38/+42
Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
2022-11-15clk: microchip: mpfs: fix reference clock handlingConor Dooley3-1/+149
The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
2022-11-15clk: microchip: mpfs: convert parent rate acquistion to get_get_rate()Conor Dooley5-35/+20
Currently the clock driver for PolarFire SoC takes a very naive approach to the relationship between clocks. It reads the dt to get an input clock, assumes that that is fixed frequency, reads the "clock-frequency" property & uses that to set up both the "cfg" and "periph" clocks. Simplifying for the sake of incremental fixes, the "correct" parentage for the clocks currently supported in U-Boot is that the "cfg" clocks should be children of the fixed frequency clock in the dt. The AHB clock is one of these "cfg" clocks and is the parent of the "periph" clocks. Instead of passing the clock rate of the fixed-frequency clock to the "cfg" and "periph" registration functions and the name of the parents, pass their actual parents & use clk_get_rate() to determine their parents rates. The "periph" clocks are purely gate clocks and should not be reading the AHB clocks registers to determine their rates, as they can simply report the output of clk_get_rate() on their parent. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
2022-11-14Merge tag 'u-boot-imx-20221114' of ↵Tom Rini5-6/+16
https://gitlab.denx.de/u-boot/custodians/u-boot-imx For 2022.01 ----------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14083 - Fix UART - moved to binman (MX8 boards) - Toradex: sync DTS with Linux - Gateworks: fixes - New boards : MSC SM2S iMX8MP
2022-11-14i2c: i2c-gpio: add newlineSergei Antonov1-1/+1
Add newline at the end of the printed string. Signed-off-by: Sergei Antonov <saproj@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2022-11-14i2c: microchip: fix erroneous late ack sendConor Dooley1-1/+1
A late ack is currently being sent at the end of a transfer due to incorrect logic in mchp_corei2c_empty_rx(). Currently the Assert Ack bit is being written to the controller's control reg after the last byte has been received, causing it to sent another byte with the ack. Instead, the AA flag should be written to the control register when the penultimate byte is read so it is sent out for the last byte. Reported-by: Andreas Buerkler <andreas.buerkler@enclustra.com> Fixes: 0dc0d1e094 ("i2c: Add Microchip PolarFire SoC I2C driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de> Removed Tag by hs: Fixes: 0190d48488 ("i2c: microchip: fix ack sending logic")
2022-11-14i2c: microchip: fix ack sending logicConor Dooley1-6/+17
"Master receive mode" was not correctly sending ACKs/NACKs in the interrupt handler. Bring the handling of M_SLAR_ACK, M_RX_DATA_ACKED & M_RX_DATA_NACKED in line with the Linux driver. Fixes: 0dc0d1e094 ("i2c: Add Microchip PolarFire SoC I2C driver") Reported-by: Shravan Chippa <shravan.chippa@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2022-11-12Revert "serial: mxc: have putc use the TXFIFO"Fabio Estevam1-1/+1
This reverts commit c7878a0483c59c48a730123bc0f4659fd40921bf. Since commit c7878a0483c5 ("serial: mxc: have putc use the TXFIFO"), serial console corruption can be seen when priting inside board_init(). Revert it to avoid the regression. Reported-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Fabio Estevam <festevam@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com>
2022-11-10global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespaceTom Rini29-84/+84
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10global: Migrate CONFIG_SYS_MPC8* symbols to the CFG_SYS namespaceTom Rini15-41/+41
Migrate all of COFIG_SYS_MPC* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-07-15 02:56:21 +0000