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2013-05-05usb: Add new command to set USB 2.0 port test modesJulius Werner1-11/+14
This patch adds a new 'usb test' command, that will set a port to a USB 2.0 test mode (see USB 2.0 spec 7.1.20). It supports all five test modes on both downstream hub ports and ordinary device's upstream ports. In addition, it supports EHCI root hub ports. Signed-off-by: Julius Werner <jwerner@chromium.org>
2013-05-05USB: EHCI: Add weak functions to support new chipJim Lin1-12/+28
Add ehci_get_port_speed() and ehci_set_usbmode() weak functions for platform driver to support new chip. Signed-off-by: Jim Lin <jilin@nvidia.com>
2013-05-02fman/mEMAC: set SETSP bit in IF_MODE regisgter for RGMII speedZang Roy-R619111-0/+17
Some legacy RGMII phys don't have in band signaling for the speed information. so set the RGMII MAC mode according to the speed got from PHY. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Reported-by: John Traill <john.traill@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-01lib: consolidate hang()Andreas Bießmann1-9/+0
Delete all occurrences of hang() and provide a generic function. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net> [trini: Modify check around puts() in hang.c slightly] Signed-off-by: Tom Rini <trini@ti.com>
2013-05-01part/dev_desc: Add log2 of blocksize to block_dev_desc data structEgbert Eich4-0/+5
log2 of the device block size serves as the shift value used to calculate the block number to read in file systems when implementing avaiable block sizes. It is needed quite often in file systems thus it is pre-calculated and stored in the block device descriptor. Signed-off-by: Egbert Eich <eich@suse.com>
2013-05-01mmc: Define a constant for the maximum block sizeSimon Glass1-12/+13
The number 512 appears quite a bit in the mmc code. Add a constant for this so that it can be used here and in other parts of the code (e.g. SPL code which loads from mmc). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@google.com>
2013-05-01spl_mmc: cleanup variable typesPeter Korsgaard1-8/+9
block_read returns unsigned long, so it doesn't make sense to check for < 0. and neither does marking the header structure as const and then casting away the constness to load data into it. Also cleanup some unneeded pointer casting while we're at it. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com> Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30watchdog: Add support for Xilinx Microblaze watchdogMichal Simek2-0/+88
Watchdog can be used on Microblaze, PPC and Zynq hw designs. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
2013-04-17mmc: check the revision for sd3.0Jaehoon Chung1-0/+2
Support to check whether the SD3.0 or not. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Rommel Custodio <sessyargc@gmail.com>
2013-04-17mmc: support the correct card version for eMMCJaehoon Chung1-0/+18
eMMC vesrion is supported up to v4.5. But bootloader isn't saw the exact eMMC version. After applied this patch, if use the mmcinfo command, then can see the exactly mmc version. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Rommel Custodio <sessyargc@gmail.com>
2013-04-15Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini31-915/+1948
2013-04-15Merge branch 'tpm' of git://git.denx.de/u-boot-x86Tom Rini7-5/+1416
2013-04-14Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD1-5/+3
2013-04-14fsl_esdhc: Fix DMA transfer completion waiting loopAndrew Gabbasov1-2/+1
Rework the waiting for transfer completion loop condition to continue waiting until both Transfer Complete and DMA End interrupts occur. Checking of DLA bit in Present State register looks not needed in addition to interrupts status checking, so it can be removed from the condition. Also, DMA Error condition is added to the list of data errors, checked in the loop. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2013-04-14fsl_esdhc: flush cache after IO completionEric Nelson1-3/+2
The cache should invalidate the read buffer for the SD card interface after the transfer complete, not command-complete. Tested-by: Andrew Gabbasov <Andrew_Gabbasov@mentor.com> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-04-14Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD1-8/+9
2013-04-13spi: mxc_spi: Set master mode for all channelsFabio Estevam1-8/+9
The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi clock glitch durant reset) solved, is back now and itwas re-introduced by commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling). Actually the glitch is happening due to always toggling between slave mode and master mode by configuring the CHANNEL_MODE bits in this reset function. Since the spi driver only supports master mode, set the mode for all channels always to master mode in order to have a stable, "glitch-free" SPI clock line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-12tpm: Add Infineon slb9635_i2c TPM driverRong Chang6-0/+1411
Add a driver for the I2C TPM from Infineon. Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2013-04-12tpm: Add casts for proper compilationTaylor Hutt1-5/+5
When building for the Sandbox version, the casts in this change are necessary to avoid compilation issues. Signed-off-by: Taylor Hutt <thutt@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2013-04-12Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD96-977/+2396
Conflicts: drivers/video/exynos_fb.c
2013-04-12Revert "mtd: cfi_flash: Fix CFI flash driver for 8-bit bus support"Stefan Roese1-55/+23
This reverts commit 239cb9d904cfa8ab50d840a47b3306189d695c75. Signed-off-by: Stefan Roese <sr@denx.de>
2013-04-12Revert "cfi_flash: Use uintptr_t for casts from u32 to void *"Stefan Roese1-1/+1
This reverts commit 81a4f7098ba137ea1961cb997ca16d57de2b3483. Signed-off-by: Stefan Roese <sr@denx.de>
2013-04-12kirkwood_nand: allow usage of NAND_ECC_SOFT_BCHGerlando Falauto1-0/+4
If CONFIG_NAND_ECC_BCH is set use 4-bit error correction code instead of the 1-bit error correction code on the NAND device. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Scott Wood <scottwood@freescale.com>
2013-04-12arm: Remove support for unused s3c64xxBenoît Thébaudeau10-593/+4
Following the removal of the smdk6400 board, the s3c64xx SoC becomes unused, so remove associated code. It will still be possible to restore it later from the Git history if necessary. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12nand: mxc: Switch NAND SPL to generic SPLBenoît Thébaudeau4-5/+597
This also fixes support for mx31pdk and tx25, which had been broken by commit e05e5de7fae5bec79617e113916dac6631251156. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-12nand: mxc: Use appropriate page number in syndrome functionsBenoît Thébaudeau1-3/+3
The syndrome functions should use the page number passed as argument instead of the page number saved upon NAND_CMD_READ0. This does not make any difference if the NAND_NO_AUTOINCR option is set, but otherwise this fixes accesses to the wrong pages. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com>
2013-04-12nand: mxc: Fix debug trace in mxc_nand_read_oob_syndrome()Benoît Thébaudeau1-1/+1
The page number indicated in the debug trace of mxc_nand_read_oob_syndrome() did not match the page being worked on. By the way, replace the GCC-specific __FUNCTION__ with __func__. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com>
2013-04-12nand: mxc: Add support for i.MX5Benoît Thébaudeau1-11/+108
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-12nand: mxc: Prepare to add support for i.MX5Benoît Thébaudeau1-46/+46
Add some abstraction to NFC definitions so that some parts of the current code can also be used for future i.MX5 code. Clean up a few things by the way. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-12mtd: nand: mxc_nand: Fix is_16bit_nand()Fabio Estevam1-34/+3
Currently is_16bit_nand() is a per SoC function and it decides the bus nand width by reading some boot related registers. This method works when NAND is the boot medium, but does not work if another boot medium is used. For example: booting from a SD card and then using NAND to store the environment variables, would lead to the following error: NAND bus width 16 instead 8 bit No NAND device found!!! 0 MiB Use CONFIG_SYS_NAND_BUSWIDTH_16BIT symbol to decide the bus width. If it is defined in the board file, then consider 16-bit NAND bus-width, otherwise assume 8-bit NAND is used. This also aligns with Documentation/devicetree/bindings/mtd/nand.txt, which states: nand-bus-width : 8 or 16 bus width if not present 8 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12mtd: nand: Introduce CONFIG_SYS_NAND_BUSWIDTH_16BITFabio Estevam1-2/+2
Introduce CONFIG_SYS_NAND_BUSWIDTH_16BIT option so that other NAND controller drivers could use it when a 16-bit NAND is deployed. drivers/mtd/nand/ndfc has CONFIG_SYS_NDFC_16BIT, so just rename it, so that other NAND drivers could reuse the same symbol. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-11ubi: ubifs: Turn off verbose printsJoe Hershberger2-6/+12
The prints are out of control. SILENCE! Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2013-04-11ubi: Fix broken cleanup code in attach_by_scanningJoe Hershberger2-4/+5
The unwind code was not reversing operations correctly and was causing a hang on any error condition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2013-04-10dfu: NAND specific routines for DFU operationPantelis Antoniou3-0/+196
Support for NAND storage devices to work with the DFU framework. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Scott Wood <scottwood@freescale.com>
2013-04-10nand: Extend nand_(read|write)_skip_bad with *actual and limit parametersTom Rini1-8/+60
We make these two functions take a size_t pointer to how much space was used on NAND to read or write the buffer (when reads/writes happen) so that bad blocks can be accounted for. We also make them take an loff_t limit on how much data can be read or written. This means that we can now catch the case of when writing to a partition would exceed the partition size due to bad blocks. To do this we also need to make check_skip_len count not just complete blocks used but partial ones as well. All callers of nand_(read|write)_skip_bad are adjusted to call these with the most sensible limits available. The changes were started by Pantelis and finished by Tom. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Tom Rini <trini@ti.com>
2013-04-10dfu: Support larger than memory transfers.Pantelis Antoniou2-89/+262
Previously we didn't support upload/download larger than available memory. This is pretty bad when you have to update your root filesystem for example. This patch removes that limitation (and the crashes when you transfered any file larger than 4MB) by making raw image writes be done in chunks and making file maximum size be configurable. The sequence number is a 16 bit counter; make sure we handle rollover correctly. This fixes the wrong transfers for large (> 256MB) images. Also utilize a variable to handle initialization, so that we don't rely on just the counter sent by the host. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Tom Rini <trini@ti.com>
2013-04-08dfu:ext4:fix: Change ext4write command order of parametersŁukasz Majewski1-2/+2
Following commit: "cmd_ext4: BREAK and correct ext4write parameter order" SHA1:0171d52c410cbaa9290b1b214e695697c835bfe5 introduced cleanup of ext4write semantics to be consistent with other filesystem's writing commands (e.g. fatwrite). This commit provides correct ext4write command generation at DFU eMMC code. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2013-04-08omap_gpmc: add support for hw assisted BCH8Andreas Bießmann1-91/+276
The kernel states: ---8<--- The OMAP3 GPMC hardware BCH engine computes remainder polynomials, it does not provide automatic error location and correction: this step is implemented using the BCH library. --->8--- And we do so in u-boot. This implementation uses the same layout for BCH8 but it is fix. The current provided layout does only work with 64 Byte OOB. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Cc: Ilya Yanok <ilya.yanok@cogentembedded.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Mansoor Ahamed <mansoor.ahamed@ti.com> Cc: Thomas Weber <thomas.weber.linux@googlemail.com>
2013-04-08omap_gpmc: change nandecc commandAndreas Bießmann1-26/+31
With uppcoming BCH support on OMAP devices we need to decide between differnt algorithms when switching the ECC engine. Currently we support 1-bit hammign and 8-bit BCH on HW backend. In order to switch between differnet ECC algorithms we need to change the interface of omap_nand_switch_ecc() also. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Cc: Thomas Weber <thomas.weber.linux@googlemail.com>
2013-04-08asm/omap_gpmc.h: consolidate common definesAndreas Bießmann1-1/+1
arch/arm/include/asm/arch-am33xx/omap_gpmc.h and arch/arm/include/asm/arch-omap3/omap_gpmc.h are almost the same, consolidate the common parts into a new header. Introduce a new asm/omap_gpmc.h which defines the command part and pulls in the architecture specific one. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
2013-04-08omap3_beagle: Flush UART3 xmit on enable if TEMT is brokenManfred Huber1-2/+16
Flush UART3 xmit on enable if TEMT is broken On some OMAP3 devices when UART3 is configured for boot mode before SPL starts only THRE bit is set. We have to empty the transmitter before initialization starts. This patch avoids the use of CONFIG_SYS_NS16550_BROKEN_TEMT. Signed-off-by: Manfred Huber <man.huber@arcor.de> Tested-by: Javier Martinez Canillas <javier@dowhile0.org> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-04-08musb: set MUSB speed based on CONFIGBin Liu2-1/+3
Do not config MUSB to highspeed mode if CONFIG_USB_GADGET_DUALSPEED is not set, in which case Ether gadget only operates in fullspeed. Reviewed-by: Tom Rini <trini@ti.com> Signed-off-by: Bin Liu <b-liu@ti.com>
2013-04-08musb: am335x: disable bulk split-combine featureBin Liu1-0/+5
On TI AM335x devices, MUSB has bulk split/combine feature enabled in the ConfigData register, but the current MUSB driver does not support it yet. Therefore, disable the feature for now, until the driver adds the support. One usecase which is broken because of this feature is that Ether gadget stops working in Fullspeed mode (by un-defining CONFIG_USB_GADGET_DUALSPEED) After desabled this feature, MUSB driver send packets in proper size (no more than 64 bytes) in Fullspeed mode. This has been validated with Ether gadget in Fullspeed mode on AM335x EVM. Signed-off-by: Bin Liu <b-liu@ti.com>
2013-04-04Merge branch 'master' of git://www.denx.de/git/u-boot-cfi-flashTom Rini1-23/+78
2013-04-04Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD9-88/+832
2013-04-04Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2-4/+11
2013-04-04spi: mxc_spi: Fix ECSPI reset handlingDirk Behme1-4/+4
Reviewing the ECSPI reset handling shows two issues: 1. For the enable/reset bit (MXC_CSPICTRL_EN) in the control reg (ECSPIx_CONGREG) the i.MX6 technical reference manual states: -- cut -- ECSPIx_CONREG[0]: EN: Writing zero to this bit disables the block and resets the internal logic with the exception of the ECSPI_CONREG. -- cut -- Note the exception mentioned: The CONREG itself isn't reset. Fix this by manually writing the reset value 0 to the whole register. This sets the EN bit to zero, too (i.e. includes the old ~MXC_CSPICTRL_EN). 2. We want to reset the whole SPI block here. So it makes no sense to first read the old value of the CONREG and write it back, later. This will give us the old (historic/random) value of the CONREG back. And doesn't reset the CONREG. To get a clean CONREG after the reset of the block, too, don't use the old (historic/random) value of the CONREG while doing the reset. And read the clean CONREG after the reset. This was found while working on a SPI boot device where the i.MX6 boot ROM has already initialized the SPI block. The initialization by the boot ROM might be different to what the U-Boot driver wants to configure. I.e. we need a clean reset of SPI block, including the CONREG. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-04ARM: bcm2835: fix get_timer() to return msStephen Warren1-2/+3
Apparently, CONFIG_SYS_HZ must be 1000. Change this, and fix the timer driver to conform to this. Have the timer implementation export a custom API get_timer_us() for use by the BCM2835 MMC API, which needs us resolution for a HW workaround. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2013-04-04cfi_flash: Use uintptr_t for casts from u32 to void *Stefan Roese1-1/+1
This fixes this build warning: Configuring for qemu_mips64 - Board: qemu-mips64, Options: SYS_BIG_ENDIAN text data bss dec hex filename 215344 13082 218720 447146 6d2aa qemu_mips64/u-boot cfi_flash.c: In function 'flash_map': cfi_flash.c:217:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@ti.com>
2013-04-03mmc: i.MX6: fsl_esdhc: Define maximum bus width supported by a boardAbbas Raza1-0/+7
Maximum bus width supported by some i.MX6 boards is not 8bit like others. In case where both host controller and card support 8bit transfers, they agree to communicate on 8bit interface while some boards support only 4bit interface. Due to this reason the mmc 8bit default mode fails on these boards. To rectify this, define maximum bus width supported by these boards (4bit). If max_bus_width is not defined, it is 0 by default and 8bit width support will be enabled in host capabilities otherwise host capabilities are modified accordingly. It is tested with a MMCplus card. Signed-off-by: Abbas Raza <Abbas_Raza@mentor.com> cc: stefano Babic <sbabic@denx.de> cc: Andy Fleming <afleming@gmail.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
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