aboutsummaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)AuthorFilesLines
2019-01-24net: move ether_crc to tsec driverChris Packham1-0/+25
ether_crc was added to the core net code in commit 53a5c424bf86 ("multicast tftp: RFC2090") so that other drivers could use it. However the only current user of it is tsec.c so move it there. Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: phy: realtek: Add functions to read PHY's extended registersCarlo Caione1-0/+29
According to the datasheet to access the extended registers we have to: 1. Write Register 31 Data = 0x0XYZ (Page 0xXYZ) 2. Read/Write the target Register Data 3. Write Register 31 Data = 0x0000 or 0xa42 (switch back to IEEE Standard Registers) Hook the missing functions so that we can use the `mdio rx/wx` command to easily access the extended registers. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: macb: fix mapping of registersRamon Fried1-1/+3
Some architectures (MIPS) needs mapping to access IOMEM. Fix that. Fixes: f1dcc19b213d ("net: macb: Convert to driver model") Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: mvneta: Add GPIO configuration supportAditya Prayoga1-0/+15
This patch add GPIO configuration support in mvneta driver. Driver will handle PHY reset. GPIO pins should be set in device tree. Ported from mvpp2x [https://patchwork.ozlabs.org/patch/799654/] Initial discussion to port the changes into mvneta [https://patchwork.ozlabs.org/patch/1005765/] Signed-off-by: Aditya Prayoga <aditya@kobol.io> Tested-by: Dennis Gilmore <dgilmore@redhat.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: mvgbe: fallback phy-mode to GMIIChris Packham1-4/+2
Some existing device trees don't specify a phy-mode so fallback to GMII when a phy-mode is not provided. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: phy: micrel: fix KSZ9031 clock skew for values greater 0psAndreas Pretzsch1-2/+2
For KSZ9021, all skew register fields are 4-bit wide. For KSZ9031, the clock skew register fields are 5-bit wide. The common code in ksz90x1_of_config_group calculating the combined register value checks if the requested value is above the maximum and uses this maximum if so. The calculation of this maximum uses the register width, but the check itself does not. It uses a hardcoded value of 0xf, which is too low in case of the 5-bit clock (0x1f). This detail was probably lost during driver unification. Effect (only for KSZ9031 clock skews): For values greater 900 (== 0ps), this silently results in 1860 (== +960ps) instead of the requested one. Fix the check by using the bit width instead of hardcoded value(s). Signed-off-by: Andreas Pretzsch <apr@cn-eng.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: mvpp2: mdio device per portBaruch Siach1-36/+33
Current code forces all ports on a given Ethernet device to use the same mdio device. In practice different ports might be wired to separate mdio devices. Move the mdio device from the container struct mvpp2 to the per port struct mvpp2_port. Cc: Ken Ma <make@marvell.com> Cc: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: mvpp2: fix lookup of mdio registers base addressBaruch Siach1-10/+7
Current mdio base lookup code relies on a 'reg' property at the upper CP node. There is no 'reg' property there in current DT files of Armada CP110. Use ofnode_get_addr() instead since it provides proper DT address translation. Cc: Ken Ma <make@marvell.com> Cc: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: designware: clear padding bytesSimon Goldschmidt1-2/+4
Short frames are padded to the minimum allowed size of 60 bytes. However, the designware driver sends old data in these padding bytes. It is common practice to zero out these padding bytes ro prevent leaking memory contents to other hosts. Fix the padding code to zero out the padded bytes at the end. Tested on socfpga gen5. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: designware: fix tx packet lengthSimon Goldschmidt1-5/+7
The designware driver has a bug in setting the tx length into the dma descriptor: it always or's the length into the descriptor without zeroing out the length mask before. This results in occasional packets being transmitted with a length greater than they should be (trailer). Due to the nature of Ethernet allowing such a trailer, most packets seem to be parsed fine by remote hosts, which is probably why this hasn't been noticed. Fix this by correctly clearing the size mask before setting the new length. Tested on socfpga gen5. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-24net: phy: Add clause 45 identifier to phy_devicePankaj Bansal1-5/+10
The phy devices can be accessed via clause 22 or via clause 45. This information can be deduced when we read phy id. if the phy id is read without giving any MDIO Manageable Device Address (MMD), then it conforms to clause 22. otherwise it conforms to clause 45. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-23pinctrl: mscc: Add gpio and pinctrl for Serval SoC family.Horatiu Vultur3-0/+244
The Serval SoC family has 32 pins. Currently there is no support for Serval in Linux kernel. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-23pinctrl: mscc: Add gpio and pinctrl for Servalt SoC family.Horatiu Vultur3-0/+279
The Servalt SoC family has 36 pins. Currently there is not support for Servalt pinctrl in Linux kernel. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-23net: add MSCC Ocelot switch supportGregory CLEMENT3-0/+773
This patch adds support for the Microsemi Ethernet switch present on Ocelot SoCs. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-21Merge git://git.denx.de/u-boot-marvellTom Rini1-42/+67
- Sync Armada-38x dts with Linux 4.20 from Chris - Misc changes and enhancements to Turris Mox (v4) from Marek - Reserve PSCI area for Armada 8k from Heinrich - New Allied Telesis x530 board (Armada-385) from Chris - Misc minor changes (defconfig etc)
2019-01-21ARM: at91: Convert SPL_GENERATE_ATMEL_PMECC_HEADER to KconfigDerald D. Woods1-0/+38
This commit converts the following items to Kconfig: CONFIG_ATMEL_NAND_HWECC CONFIG_ATMEL_NAND_HW_PMECC CONFIG_PMECC_CAP CONFIG_PMECC_SECTOR_SIZE CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER [PMECC References] https://www.at91.com/linux4sam/bin/view/Linux4SAM/PmeccConfigure https://www.at91.com/linux4sam/bin/view/Linux4SAM/AT91Bootstrap [Mailing List Thread] https://lists.denx.de/pipermail/u-boot/2018-December/350666.html Fixes: 5541543f ("configs: at91: Remove CONFIG_SYS_EXTRA_OPTIONS assignment") [trini: Make the migration be size neutral and possibly not fix the above in all cases] Reported-by: Daniel Evans <photonthunder@gmail.com> Cc: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Derald D. Woods <woods.technical@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-21watchdog: armada_37xx: Fix compliance with kernel's driverMarek Behún1-42/+67
The Armada 37xx watchdog driver was recently accepted for mainline kernel by watchdog subsystem maintainer, but the driver works a little different than the one in U-Boot. This patch fixes this. In the previous implementation there was a tiny period of time when the watchdog was disabled and the system was vulnerables - this was during pinging, which was done by disabling, setting, and enabling the counter. Now pinging is done without disabling the watchdog. We use 2 counters: Counter 1 is the watchdog counter - on expiry, the system is reset. Counter 0 is used to reset Counter 1 to start counting from the set timeout again. So Counter 1 is set to be reset on Counter 0 expiry event event and pinging is done by forcing an immediate expiry event on Counter 0. Signed-off-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-19Kconfig: Migrate BOUNCE_BUFFERPhilipp Tomsich1-0/+3
The bounce buffer is used by a few drivers (most of the MMC drivers) to overcome limitations in their respective DMA implementation. This moves the configuration to Kconfig and makes it user-selectable (even though it will be a required feature to make those drivers work): the expected usage is for drivers depending on this to 'select' it unconditionally from their respective Kconfig (see follow-up patches). This commit includes a full migration using moveconfig.py to ensure that each commit compiles. To ensure bisectability we update dependencies of various drivers to now select BOUNCE_BUFFER when needed. [trini: Squash all patches to ensure bisectability] Signed-off-by: Tom Rini <trini@konsulko.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Otavio Salvador <otavio@ossystems.com.br> [dw_mmc portion] Reviewed-by: Fabio Estevam <festevam@gmail.com> [mxsmmc portion] Reviewed-by: Simon Glass <sjg@chromium.org> [tegra portion]
2019-01-18Merge tag 'fsl-qoriq-for-v2019.04-rc1' of git://git.denx.de/u-boot-fsl-qoriqTom Rini6-13/+213
Add TFA boot flow for more boards Add TFA boot defconfig for ls1088a and ls2088a. Add dts fixup for PCIe endpoint and root complex.
2019-01-18video: Kconfig: spelling fixesChris Packham1-1/+1
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-18pinctrl: Kconfig: spelling fixesChris Packham1-1/+1
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-18i2c: Kconfig: spelling fixesChris Packham1-4/+4
Signed-off-by: Chris Packham <judge.packham@gmail.com>
2019-01-18drivers: Kconfig: spelling fixesChris Packham1-1/+1
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-17Merge tag 'mips-pull-2019-11-16' of git://git.denx.de/u-boot-mipsTom Rini17-251/+1098
- MIPS: mscc: various enhancements for Luton and Ocelot platforms - MIPS: mscc: added support for Jaguar2 platform - MIPS: optimised SPL linker script - MIPS: bcm6368: fix restart flow issues - MIPS: fixed CONFIG_OF_EMBED warnings for all MIPS boards - MIPS: mt7688: small fixes and enhancements - mmc: compile-out write support if disabled
2019-01-17pci: layerscape: Add the dts fixup for EP and RCXiaowei Bao1-2/+23
Add the dts fixup when PCI controller work diffferent mode. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17pci: layerscape: Do not scan when PEX work in EP modeXiaowei Bao1-0/+3
Don't scan the bus when the PEX work in EP mode. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17pci: layerscape: Modify the EP and RC mode judge methodXiaowei Bao2-10/+9
Modify the RC and EP mode judge method, save the mode as a variable, the variable will be used by other function. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17mmc: fsl_esdhc: make get_cd work well in dm_mmc_opsYinbo Zhu1-1/+0
This patch is to make get_cd work well when DM_MMC enabled Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17fsl-layerscape: dpaa: fix fsl-mc status in fdt with bootefiMian Yousaf Kaukab1-0/+5
fsl-mc lazyapply command applies dpl from efi_exit_boot_services(). Status of fsl-mc node in working fdt is updated at this stage. However, an efi application like grub may already have copied the fdt. So the updates to fdt done at efi_exit_boot_services() may not be visible to the OS. Fix it by updating fdt earlier if fsl-mc lazyapply command is used. Fixes: b7b8410a8f (ls2080: Exit dpaa only right before exiting U-Boot) Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17drivers: ifc: restore the legacy flow for IFC configRajesh Bhagat1-0/+173
Restore the legacy flow along with TFABOOT flow for IFC configuration. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-16mtd: nand: raw: allow to disable unneeded ECC layoutsStefan Agner2-0/+11
Each ECC layout consumes about 2984 bytes in the .data section. Allow to disable the default ECC layouts if a driver is known to provide its own ECC layout. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-01-16pinctrl: mscc: Add gpio and pinctrl for Jaguar2 SOC familyHoratiu Vultur7-29/+443
The Jaguar2 SOC family has 63 gpio pins therefore I extended mscc-common to support new numbe of pins and remove any platform dependency from mscc-common. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-16mips: gpio: mscc: Obsoleted gpio-mscc-bitbang-spi.cLars Povlsen3-130/+0
With the new mscc_bb_spi.c driver, there is no longer use for the gpio-mscc-bitbang-spi.c driver. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16mips: spi: mscc: Add fast bitbang SPI driverLars Povlsen3-0/+244
This patch add a new SPI driver for MSCC SOCs that does not sport the designware SPI hardware controller. Performance gain: 7.664 seconds vs. 17.633 for 1 Mbyte write. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16mmc: jz_mmc: Compile-out write support if disabledEzequiel Garcia1-44/+61
Do not build write support, unless it's enabled. In the SPL case, this change will typically remove precious bytes (as write support is most often not needed in SPL). This is important on this platform, where the maximum SPL size is 14 KiB. With gcc v7.3, this change saves 144 bytes producing: size spl/u-boot-spl text data bss dec hex filename 9240 752 712 10704 29d0 spl/u-boot-spl To make the code easier to compile-out and more readable, a pair of read_data/write_data helpers are created. Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16mmc: Use proper IS_ENABLED macro to check block supportEzequiel Garcia1-4/+4
Use CONFIG_IS_ENABLED(BLK) instead of CONFIG_BLK, in order to fix the following build issues when CONFIG_SPL_MMC_WRITE is selected: drivers/mmc/mmc_write.c:69:7: error: conflicting types for 'mmc_berase' ulong mmc_berase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt) ^~~~~~~~~~ In file included from drivers/mmc/mmc_write.c:15:0: drivers/mmc/mmc_private.h:39:7: note: previous declaration of 'mmc_berase' was here ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt); ^~~~~~~~~~ drivers/mmc/mmc_write.c:187:7: error: conflicting types for 'mmc_bwrite' ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, ^~~~~~~~~~ In file included from drivers/mmc/mmc_write.c:15:0: drivers/mmc/mmc_private.h:37:7: note: previous declaration of 'mmc_bwrite' was here ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, ^~~~~~~~~~ Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16net: bcm6368: fix restart flow issuesÁlvaro Fernández Rojas1-47/+62
Correctly enable/disable bcm6368-net controller to avoid flow issues. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16mips: mscc_sgpio: Add the MSCC serial GPIO device (SIO)Lars Povlsen3-0/+287
This add support for the the MSCC serial GPIO driver in MSCC VCoreIII-based SOCs. By using a serial interface, the SIO controller significantly extends the number of available GPIOs with a minimum number of additional pins on the device. The primary purpose of the SIO controller is to connect control signals from SFP modules and to act as an LED controller. This adds the base driver. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
2019-01-15Merge tag 'dm-pull-15jan19' of git://git.denx.de/u-boot-dmTom Rini3-25/+15
Fix recent changes to serial API for driver model Buildman clang support and a few fixes Small fixes to 'dm tree' and regmap test Improve sandbox build compatibility A few other minor fixes
2019-01-15Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini6-5/+358
2019-01-15misc: fs_loader: Switching private data allocation to DM auto allocationTien Fong Chee1-63/+45
Switching private data manual allocation to driver model auto allocation so users no longer need to deallocate themself because this would be deallocated by driver model when the device is no longer required. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-15blk: Increase cache element sizeMarek Vasut1-1/+1
Cache up to 4 kiB entries. 4 kiB is the default block size on ext4, yet the underlying block layer devices usually report support for 512B . In most cases, the 512B support is emulated (ie. SD cards, SSDs, USB sticks etc.) and the real block size of those devices is much bigger. To avoid performance degradation with such devices and FS setup, bump the maximum cache entry size to 4 kiB. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-15serial: ns16550: fix debug uart putc called before initSimon Goldschmidt2-2/+30
If _debug_uart_putc() is called before _debug_uart_init(), the ns16550 debug uart driver hangs in a tight loop waiting for the tx FIFO to get empty. As this can happen via a printf sneaking in before the port calls debug_uart_init(), introduce a config option to ignore characters before the debug uart is initialized. This is done by reading the baudrate divisor and aborting if is zero. The Kconfig option is required as reading the baudrate divisor does not seem to work for all ns16500 compatibles (which is why the last attempt on this has been reverted in 1a67969a99). Tested on socfpga_cyclone5_socrates. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-15drivers: serial: DEBUG_UART_SKIP_INIT depends on DEBUG_UARTSimon Goldschmidt1-0/+1
DEBUG_UART_SKIP_INIT is used only by debug UART and thus should depend on DEBUG_UART. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-15mmc: Add support for downgrading HS200/HS400 to HS modeMarek Vasut1-6/+33
The mmc_select_mode_and_width() function can be called while the card is in HS200/HS400 mode and can be used to downgrade the card to lower mode, e.g. HS. This is used for example by mmc_boot_part_access_chk() which cannot access the card in HS200/HS400 mode and which is in turn called by saveenv if env is in the MMC. In such case, forcing the card clock to legacy frequency cannot work. Instead, the card must be switched to HS mode first, from which it can then be reprogrammed as needed. However, this procedure needs additional code changes, since the current implementation checks whether the card correctly switched to HS mode in mmc_set_card_speed(). The check only expects that the card will be going to HS mode from lower modes, not from higher modes, hence add a parameter which indicates that the HS200/HS400 to HS downgrade is happening. This makes the code send the switch command first, reconfigure the controller next and finally perform the EXT_CSD readback check. The last two steps cannot be done in reverse order as the card is already in HS mode when the clock are being switched on the controller side. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com>
2019-01-15mmc: Convert HI6220 MMC driver to driver modelManivannan Sadhasivam1-31/+69
Convert HiSilicon HI6220 MMC driver based on DWMMC IP to driver model. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Enable this on poplar] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-15i2c: Reflect correct dependency for !DM cadence driverMichal Simek1-0/+1
Setup proper DM_I2C dependency. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-15i2c: mux: Covert to livetree functionsMichal Simek2-4/+2
Updates i2c muxes drivers to support livetree. Similar changes were done by: "net: zynq_gem: convert to use livetree" (sha1: 26026e695afa794ac018a09e79a48120d322b60d) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-15i2c: i2c-cdns: Use proper input frequencyTomasz Gorochowik1-1/+8
This is needed to properly calculate i2c bus speed divisors. Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com> Signed-off-by: Wojciech Tatarski <wtatarski@antmicro.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-15i2c: xiic: Add Xilinx AXI I2C driverMarek Vasut3-0/+347
Add Xilinx AXI I2C controller driver based on the Linux i2c-xiic driver. This driver is stripped of all the IRQ handling and uses pure polling, yet tries to retain most of the structure of the Linux driver to make backporting of fixes easy. Note that the IP has a known limitation on 255 bytes read and write, according to xilinx this is still being worked on [1]. [1] https://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI-IIC-V2-0-I2C-Master-Reading-multiple-bytes-from-I2C-slave/m-p/854419/highlight/true#M39387 Signed-off-by: Marek Vasut <marex@denx.de> Cc: Michal Simek <monstr@monstr.eu> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de>
generated by cgit v1.1 at 2024-07-15 09:27:45 +0000