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path: root/drivers/video/ipu_common.c
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2018-01-03video: ipu: Fix dereferencing NULL pointer problemPeng Fan1-1/+5
The clk_set_rate function dereferences the clk pointer without checking whether it is NULL. This may cause problem when clk is NULL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-09-11ipu_common: Let the MX6 IPU clock be calculated in run-timeFabio Estevam1-1/+13
MX6Q/QP IPU operates at 264MHz and MX6DL IPU at 198MHz. When running a SPL target, which supports multiple MX6 variants we cannot properly setup the IPU clock frequency via CONFIG_IPUV3_CLK option as such decision is done in build-time currently. Remove the CONFIG_IPUV3_CLK option and let the IPU clock frequency be configured in run-time on mx6. Reported-by: Eric Nelson <eric@nelint.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com> Reviewed-by: Stefano Babic <sbabic@denx.de> [agust: fixed #endif in cgtqmx6eval.h] Signed-off-by: Anatolij Gustschin <agust@denx.de>
2017-09-04video: ipuv3_fb: skip IPU shutdown if IPU was not enabled beforeAnatolij Gustschin1-0/+5
Boards can skip display interface init using board_video_skip(). If display interface was not initialized (e.g. no ipuv3 framebuffer registered or IPU clock disabled), booting Linux stops due to the crash in IPU shutdown function, when accessing IPU registers. Check IPU clock and skip shutdown if clock is not enabled. Signed-off-by: Anatolij Gustschin <agust@denx.de>
2016-09-23treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada1-1/+1
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-04-28video: ipu_common: fix build errorPeng Fan1-1/+3
Some toolchains fail to build "clk->rate = (u64)(clk->parent->rate * 16) / div;" And the cast usage is wrong. Use the following code to fix the issue, " do_div(parent_rate, div); clk->rate = parent_rate; " Reported-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Tom Rini <trini@konsulko.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Peter Robinson <pbrobinson@gmail.com>
2016-03-14video: ipu: avoid overflow issuePeng Fan1-19/+54
Multiplication, as "clk->parent->rate * 16" may overflow. So use do_div to avoid such issue. Signed-off-by: Peng Fan <van.freenix@gmail.com> Signed-off-by: Sandor Yu <sandor.yu@nxp.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
2015-04-20video, ipu: make ldb clock frequency overwritable through board codeHeiko Schocher1-0/+8
the ldb clock can be setup in board code (for example set through PLL5). Update the ldb_clock rate also through board code. This should be removed, if a clock framework is availiable. Signed-off-by: Heiko Schocher <hs@denx.de> Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
2015-04-20video, ipu: make ldb_clock configurableHeiko Schocher1-1/+5
make the ldb_clock configurable through the new define CONFIG_SYS_LDB_CLOCK. This is needed as the ldb clock is not always 650000000, for example on the aristainetos2 board, where the ldb clock derives from PLL5 clock. Signed-off-by: Heiko Schocher <hs@denx.de> Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
2014-10-25video: ipu: prevent warnings with W=1Jeroen Hofstee1-1/+1
- make local functions static - remove unused is_interlaced function Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2013-07-24Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk1-17/+1
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
2012-11-06ipu common: reset ipuv3 correctlyLiu Ying1-0/+10
This patch checks self-clear sw_ipu_rst bit in SCR register of SRC controller to be cleared after setting it to high to reset IPUv3. This makes sure that IPUv3 finishes sofware reset. A timeout mechanism is added to stop polling on the bit status in case the bit could not be cleared by the hardware automatically within 10 millisecond. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-10-15mx5: Use explicit clock gate namesBenoît Thébaudeau1-1/+1
Use clock gate definitions having names showing clearly the gated clock instead of names giving only a register field index. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
2012-10-15i.MX6: provide functional names for CCM_CCGR0-CCGR6 bit fieldsEric Nelson1-2/+8
Add meaningful constants for each clock channels and use them for enabling and disabling i.MX6 clocks. Includes an update to enable/disable the IPU1 clock in drivers/video/ipu_common to remove IMX5x register access when used on i.MX6 as discussed in V1: http://patchwork.ozlabs.org/patch/185129/ Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-07-10ipu_common: Add ldb_clk for use in parenting the pixel clockEric Nelson1-2/+10
Add ldb_clk for use in parenting the pixel clock. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-10ipu_common: Do not hardcode the ipu_clk frequencyFabio Estevam1-1/+1
Do not hardcode the ipu_clk frequency and let the board file pass this value. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-10ipu_common: Rename MXC_CCM_BASEFabio Estevam1-1/+1
Rename MXC_CCM_BASE to CCM_BASE_ADDR as this is already defined for MX6. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-10ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53Fabio Estevam1-1/+4
The registers accessed inside clk_ipu_enable/disable are not present on MX6, so make sure they only run on MX51 and MX53. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-10ipu_common: Only apply the erratum to MX51Fabio Estevam1-0/+2
The following erratum : "ENGcm08316 IPU: Clarification regarding the bypass mode registers setup for display and camera interfaces" only applies to mx51, so restrict its usage for this SoC only. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2010-10-22MX51: Add IPU driver for video supportStefano Babic1-0/+1183
The patch is a porting of the IPU Linux driver developed by Freescale to have framebuffer functionalities in u-boot. The port is based on kernel 2.6.31 commit cc4fe714041805997b601fe8e5dd585d8a99297f, as delivered by Freescale [i.MX BSP]. Most features are dropped from the original driver and only LCD support is the goal of this porting. Signed-off-by: Stefano Babic <sbabic@denx.de>
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