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path: root/drivers/timer
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2024-01-29treewide: Remove clk_freeSean Anderson2-4/+0
This function is a no-op. Remove it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20231216193843.2463779-3-seanga2@gmail.com
2023-12-21global: Restrict use of '#include <linux/kconfig.h>'Tom Rini1-1/+0
In general terms, we -include include/linux/kconfig.h and so normal U-Boot code does not need to also #include it. However, for code which is shared with userspace we may need to add it so that either our full config is available or so that macros such as CONFIG_IS_ENABLED() can be evaluated. In this case make sure that we guard these includes with a test for USE_HOSTCC so that it clear as to why we're doing this. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-18timer: starfive: Add Starfive timer supportKuan Lim Lee1-7/+9
Add timer driver in Starfive SoC. It is an timer that outside of CPU core and inside Starfive SoC. Signed-off-by: Kuan Lim Lee <kuanlim.lee@starfivetech.com> Signed-off-by: Wei Liang Lim <weiliang.lim@starfivetech.com> Changes for v2: - correct driver name, comment, variable Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-11-29timer-uclass: Always use "clock-frequency" property as fallbackAlex Bee1-6/+6
Currently the "clock-frequency" DT property is only being considered as an fallback if either there is no clock driver, the clock driver implements the request-op correctly or there is no clock defined for the timer at all. This patch makes "clock-frequency" also being picked as a fallback if getting the clock-rate fails, since clk_get(_by_index) will return no error, if a clock driver does not implement the request-op and does also not support getting the rate of the clock in question. timer_post_probe will take care if the property does not exist in the DT or is defined as 0. Signed-off-by: Alex Bee <knaerzche@gmail.com>
2023-10-04riscv: andesv5: Prefer using the generic RISC-V timer driver in S-modeYu Chien Peter Lin2-2/+9
The Andes PLMT driver directly accesses the mtime MMIO region, indicating its intended use in the M-mode boot stage. However, since U-Boot proper (S-mode) also uses the PLMT driver, we need to specifically mark the region as readable through PMPCFGx (or S/U-mode read-only shared data region for Smepmp) in OpenSBI. Granting permission for this case doesn't make sense. Instead, we should use the generic RISC-V timer driver to read the mtime through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER config, which ensures that the PLMT driver is linked exclusively against M-mode U-Boot or U-Boot SPL binaries. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
2023-10-04timer: starfive: Add Starfive timer supportKuan Lim Lee3-0/+102
Add timer driver in Starfive SoC. It is an timer that outside of CPU core and inside Starfive SoC. Signed-off-by: Kuan Lim Lee <kuanlim.lee@starfivetech.com> Reviewed-by: Wei Liang Lim <weiliang.lim@starfivetech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-04timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGEChanho Park1-0/+23
timer_get_boot_us function is required to record the boot stages as us-based timestamp. To get a micro-second time from a timer tick, this converts the formula like below to avoid zero result of (tick / rate) part. From: time(us) = (tick / rate) * 1000000 To : time(us) = (tick * 1000) / (rate / 1000) Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-04riscv: timer: add timer_get_boot_us for BOOTSTAGEChanho Park1-0/+22
timer_get_boot_us function is required to record the boot stages as us-based timestamp. To get a micro-second time from a timer tick, this converts the formula like below to avoid zero result of (tick / rate) part. From: time(us) = (tick / rate) * 1000000 To : time(us) = (tick * 1000) / (rate / 1000) Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-02Merge branch 'next'Tom Rini1-13/+0
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-09-14timer: Remove unused NEEDS_MANUAL_RELOC code bitsMarek Vasut1-13/+0
The last user of the NEEDS_MANUAL_RELOC has been removed in commit 26af162ac8f8 ("arch: m68k: Implement relocation") Remove now unused NEEDS_MANUAL_RELOC code. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-09-05riscv: allow riscv timer to be instantiated via device treeTorsten Duwe1-2/+26
For the architectural timer on riscv, there already is a defined device tree binding[1]. Allow timer instances to be created from device tree matches, but for now retain the old mechanism, which registers the timer biggy-back with the CPU. [1] linux/Documentation/devicetree/bindings/timer/riscv,timer.yaml Signed-off-by: Torsten Duwe <duwe@suse.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-07-28omap: timer: add ti,am654-timer compatibilitySjoerd Simons1-0/+1
The TI AM654 timer is compatible with the omap-timer implementation, so add it to the compatible id list. Signed-off-by: Sjoerd Simons <sjoerd@collabora.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Maxime Ripard <mripard@kernel.org> Tested-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Cc: Francesco Dolcini <francesco@dolcini.it> Cc: Wadim Egorov <w.egorov@phytec.de> Signed-off-by: Nishanth Menon <nm@ti.com>
2023-07-12riscv: Rename SiFive CLINT to RISC-V ALINTBin Meng2-11/+11
As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-07-12riscv: timer: Update the sifive clint timer driver to support aclintBin Meng1-5/+11
This RISC-V ACLINT specification [1] defines a set of memory mapped devices which provide inter-processor interrupts (IPI) and timer functionalities for each HART on a multi-HART RISC-V platform. The RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, however the device tree binding is a new one. This change updates the sifive clint timer driver to support ACLINT mtimer device, using a per-driver data field to hold the mtimer offset to the base address encoded in the mtimer node. [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-05-06rockchip: timer: dw-apb-timer: use regs variable with uintptr_t sizeJohan Jonker1-1/+1
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use a regs variable with uintptr_t size in the dw-apb-timer.c file. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-27Merge branch 'master' into nextTom Rini1-5/+3
2023-03-19rockchip: timer: rockchip_timer: fix compatible and driver nameJohan Jonker1-5/+3
In the binding for the Rockchip timer the compatible string consists of a SoC orientated string and a fall back string "rockchip,rk3288-timer", so remove all unneeded ones and fix driver name. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-14Merge tag 'v2023.04-rc4' into nextTom Rini1-0/+2
Prepare v2023.04-rc4 Signed-off-by: Tom Rini <trini@konsulko.com>
2023-03-13efi: Use a fixed value for the timer clockSimon Glass1-0/+9
It is not yet clear how to read the timer via EFI. The current value seems much too high on a Framework laptop I tried. Adjust it to a lower hard-coded value for now. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-06timer: fttmr010: return a previously deleted driver now ported to DMSergei Antonov3-0/+100
The fttmr010 timer driver was deleted by commit 29fc6f24926e ("ARM: remove a320evb board support") The original source file was: arch/arm/cpu/arm920t/a320/timer.c Return the driver to the codebase in a DM compatible form. A platform using fttmr010 will be submitted later. This hardware is described in the datasheet [1], starting from page 348. According to the datasheet, there is a Revision Register at offset 0x3C, which is not present in 'struct fttmr010'. Add it and debug() print revision in probe function. [1] https://bitbucket.org/Kasreyn/mkrom-uc7112lx/src/master/documents/FIC8120_DS_v1.2.pdf Signed-off-by: Sergei Antonov <saproj@gmail.com>
2023-03-01sandbox: fix building with CONFIG_SPL_TIMER=yHeinrich Schuchardt1-0/+2
Building sandbox_defconfig with CONFIG_SPL_TIMER=y results in an error include/dm/platdata.h:63:33: error: static assertion failed: "Cannot use U_BOOT_DRVINFO with of-platdata. Please use devicetree instead" Add a missing condition in the sandbox driver. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-11timer: Tidy up use of notraceSimon Glass1-1/+1
Tracing is typically enabled by the time driver model starts up, so there is no point in adding a 'notrace' to the timer-init function. However, once the driver model timer is enabled, we do need to be able to access the timer's private data when reading the timer, so add it to the core function needed for that. Update the function's documentation while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-02drivers: timer: add driver for ARMv7 based Tegra devices and T210Svyatoslav Ryhel3-0/+139
Add timer support for T20/T30/T114/T124 and T210 based devices. Driver is based on DM, has device tree support and can be used on SPL and early boot stage. Arm64 Tegra (apart T210) according to comment in tegra-common.h use architected timer. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com>
2023-01-20global: Finish CONFIG -> CFG migrationTom Rini1-3/+3
At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-17timer: orion-timer: Fix problem in early_init_done()Stefan Roese1-1/+2
It was noticed that Clearfog is currently broken with this newly introduced early_init_done() function. Apparently the timer is enabled here when U-Boot is run but not configured - at least not correctly. Resulting in a hangup in the timer reading functions. To fix this, also read the value of the reload register and check it's value with the one written to by U-Boot. Only if this matches, the init has already been done. Fixes: 5387b093cb79 ("timer: orion-timer: Fix problem with early static variable") Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Pali Rohár <pali@kernel.org> Cc: Martin Rowe <martin.p.rowe@gmail.com> Cc: Tony Dinh <mibodhi@gmail.com> Cc: Pali Rohár <pali@kernel.org> Cc: Michael Walle <michael@walle.cc>
2023-01-09Merge branch 'next'Tom Rini4-10/+10
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-01-02timer: orion-timer: Fix problem with early static variableStefan Roese1-3/+7
We've noticed that at least one Kirkwood board (Pogo v4) has problems with the new orion DM timer implementation. Debugging revealed that this issue is related with the static variable "early_init_done" which does not work correctly before relocation in all cases. This patch removes this static variable and replaces it's functionality via a function that detects if the timer is already initialized. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pali Rohár <pali@kernel.org> Cc: Michael Walle <michael@walle.cc> Cc: Tony Dinh <mibodhi@gmail.com> Tested-by: Tony Dinh <mibodhi@gmail.com>
2022-12-05global: Move remaining CONFIG_SYS_* to CFG_SYS_*Tom Rini4-10/+10
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-22timer: xilinx-timer: use timer_conv_64() to fix timer wrap aroundOvidiu Panait1-1/+1
Current xilinx_timer_get_count() implementation does not take into account the periodic 32-bit wrap arounds, as it directly returns the 32-bit counter register value. The roll-overs cause problems in the upper timer layers, as generic timer code expects an incrementing 64-bit value from get_count() to work correctly. Add the missing 64-bit up-conversion to fix random hangs/delays in __udelay(). Fixes: a36d86720f ("microblaze: Convert axi timer to DM driver") Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Reviewed-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221012053656.1492457-3-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22timer-uclass: relocate ops pointers for CONFIG_NEEDS_MANUAL_RELOCOvidiu Panait1-0/+14
Relocate timer_ops pointers when CONFIG_NEEDS_MANUAL_RELOC is enabled. The (gd->flags & GD_FLG_RELOC) check was added to make sure the reloc_done logic works for drivers that use DM_FLAG_PRE_RELOC. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20221012053656.1492457-2-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22timer-uclass: add timer_get_ops() macroOvidiu Panait1-1/+1
Align timer uclass with the other subsystems and provide a timer_get_ops() convenience macro. Using this instead of the generic device_get_ops() also prevents -Wdiscarded-qualifiers warnings when used with non-const variables. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20221012053656.1492457-1-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-03Merge branch '2022-11-02-assorted-updates'Tom Rini3-0/+115
- Improve arm semihosting, NPCM8xx pinctrl driver, SP804 uclass timer driver (and enable on relevant platforms), pvblock cleanup, eeprom cmd bugfix, add RTI watchdog nodes to k3-am64-main, evb-ast2500 config updates.
2022-11-03riscv: Rename Andes PLIC to PLICSWYu Chien Peter Lin1-1/+1
As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-11-02timer: add SP804 UCLASS timer driverAndre Przywara3-0/+115
The "Arm Ltd. Dual-Timer Module (SP804)" is a simple 32-bit count-down timer IP with interrupt functionality, and is used in some SoCs from various vendors. Add a simple DM compliant timer driver, to allow users of the SP804 to switch to DM_TIMER. This relies on the input clock to be accessible via the DM clock framework, which should be fine as we probably look at fixed-clock's here anyway. We re-program the control register in the probe() function, but keep the divider in place, in case this has been set to something on purpose before. The TRM for the timer IP can be found here: https://developer.arm.com/documentation/ddi0271/latest Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-10-31timer: sti: convert sti-timer to arm a9 global timerWilliam Zhang3-18/+22
STI timer is actually ARM Cortex A9 global timer. Convert the driver to use generic global timer name and make it consistent with Linux kernel global timer driver. This also allows any A9 based device to use this driver. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-10-06timer: orion-timer: Only init timer onceStefan Roese1-5/+5
Move the code making sure that the timer is initialized only once into orion_timer_init(), which is called from timer_early_init() and from orion_timer_probe(). This way the timer is not re-initialized. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Michael Walle <michael@walle.cc> Cc: Pali Rohár <pali@kernel.org>
2022-09-23timer: mtk: add support for MediaTek MT7981/MT7986 SoCsWeijie Gao1-22/+37
This patch add general-purpose timer support for MediaTek MT7981/MT7986. These two SoCs uses a newer version of timer with its register definition slightly changed. Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-20timer: orion-timer: Add timer_get_boot_us() for BOOTSTAGE supportStefan Roese1-19/+64
Add timer_get_boot_us() to support boards, that have CONFIG_BOOTSTAGE enabled, like pogo_v4. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Tony Dinh <mibodhi@gmail.com>
2022-09-20timer: orion-timer: Add support for other Armada SoC'sStefan Roese2-4/+43
This patch adds support for other Marvell Armada SoC's, supporting the 25MHz fixed clock operation, like the Armada XP etc. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Tony Dinh <mibodhi@gmail.com>
2022-09-19Merge branch 'master' into nextTom Rini1-1/+1
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-09-18timer: orion-timer: Use timer_conv_64() to fix timer wrap aroundStefan Roese1-1/+1
While testing on some Kirkwood platforms it was noticed that the timer did not function correctly all the time. The driver did not correctly handle 32bit timer value wrap arounds. Using the timer_conv_64() conversion function fixes this issue. Fixes: e9e73d78a8fb ("timer: add orion-timer support") Suggested-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier-oss@weidmueller.com> Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Tony Dinh <mibodhi@gmail.com>
2022-09-18cyclic: Use schedule() instead of WATCHDOG_RESET()Stefan Roese1-2/+2
Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
2022-09-12zynq: Convert arm twd timer to DM driverStefan Herbrechtsmeier3-0/+115
Move arm twd timer driver from zynq to generic location. DM timer drivers are designed differently to original driver. Timer is counting up and not down. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220805061629.1207-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-08-23timer: add orion-timer supportMichael Walle3-0/+70
Add timer support for Kirkwood and MVEBU devices. Cc: Pali Rohár <pali@kernel.org> Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-06-27Merge tag 'xilinx-for-v2022.10' of ↵WIP/27Jun2022-nextTom Rini3-0/+92
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.10 cpu: - Add driver for microblaze cpu net: - Add support for DM_ETH_PHY to AXI emac and emaclite xilinx: - Switch platforms to DM_ETH_PHY - DT chagnes in ZynqMP and Zynq - Enable support for SquashFS zynqmp: - Add support for KR260 boards - Move BSS from address 0 - Move platform identification from board code to soc driver - Improve zynqmp_psu_init_minimize versal: - Enable loading app at EL1 serial: - Setup default address and clock rates for DEBUG uarts pinctrl: - Add support for tri state and output enable properties relocate-rela: - Clean relocate-rela implementation for ARM64 - Add support for Microblaze microblaze: - Add support for runtime relocation - Rework cache handling (wiring, Kconfig) based on cpuinfo - Remove interrupt support timer: - Extract axi timer driver from Microblaze to generic location
2022-06-27timer: Add SPL_REGMAP dependency for Xilinx timerMichal Simek1-0/+1
Add SPL_REGMAP dependency when SPL is enabled. This can avoid compilation issues if timer is selected but SPL_REGMAP not. Reported-by: Ovidiu Panait <ovidiu.panait@windriver.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/8f6c187e04cb3127bf5148ae2dbbdf55b25ea544.1655982509.git.michal.simek@amd.com
2022-06-24microblaze: Convert axi timer to DM driverMichal Simek3-0/+91
Move axi timer driver from Microblaze to generic location. Origin implementation was irq based with counting down timer. CONFIG_TIMER drivers are designed differently that timer is free running up timer with automatic reload without any interrupt. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Michal Simek <michal.simek@amd.com> Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com
2022-06-22timer: gxp: Add HPE GXP timer supportNick Hawkins3-0/+72
Add support for the HPE GXP SOC timer. The GXP supports several different kinds of timers but for the purpose of this driver there is only support for the General Timer. The timer has a 1us resolution and is 56 bits. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
2022-06-06arm: omap2plus: Move CONFIG_SYS_PTV out of CONFIG namespaceTom Rini1-2/+3
This is always defined to 2, and referenced in two places. Move the define to <asm/omap_common.h> and make sure the code that uses this includes that file. Make <asm/arch-omap*/clock.h> not include that file, as we don't need to be doing so. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-05timer: npcm: Add NPCM timer supportJim Liu3-0/+125
Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com>
generated by cgit v1.1 at 2024-08-12 09:55:24 +0000