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2017-11-30cosmetic: atcspi200: Rename function name as atcspi200Rick Chen1-48/+48
Integrate function and struct name from ae3xx to atcspi200 will be more reasonable. Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-30spi: nds_ae3xx: Rename nds_ae3xx_spi as atcspi200_spiRick Chen3-6/+6
atcspi200 is Andestech spi ip which is embedded in AE3XX and AE250 platforms. So rename as atcspi200 will be more reasonable to be used in different platforms. Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-21rockchip: spi: the symbol for Hertz is HzHeinrich Schuchardt1-1/+1
fix typo Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-20omap3: spi: the symbol for Hertz is HzHeinrich Schuchardt1-1/+2
fix typo Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-10-27spi: ich: Lock down controller settings if requiredBin Meng2-0/+23
Some Intel FSP (like Braswell) does SPI lock-down during the call to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done, it's bootloader's responsibility to configure the SPI controller's opcode registers properly otherwise SPI controller driver doesn't know how to communicate with the SPI flash device. Rather than passively doing the opcode configuration, let's add a simple DTS property "intel,spi-lock-down" and let the driver call the opcode configuration function if required by such FSP. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-16spi: Drop CONFIG_ATMEL_DATAFLASH_SPITuomas Tynkkynen2-185/+0
Last user of this option went away in commit: fdc7718999 ("board: usb_a9263: Update to support DT and DM") Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Acked-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-10-04treewide: replace with error() with pr_err()Masahiro Yamada2-4/+4
U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-29spi: davinci_spi: Add da830-spi support for DMAdam Ford1-0/+1
The DM support is already in the driver, so add da830-spi to the compatible list. Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-25spi: fsl_qspi: Copy 16 byte aligned data in TX FIFOSuresh Gupta1-10/+8
In some of the QSPI controller version, there must be atleast 128bit data available in TX FIFO for any pop operation otherwise error bit will be set. The code will not make any behavior change for previous controller as the transfer data size in ipcr register is still the same. Patch is tested on LS1046A which do not require 16 bytes aligned and LS1088A which require 16 bytes aligned data in TX FIFO Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Anupam Kumar <anupam.kumar_1@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-09-25spi: fsl_qspi: Add controller busy check before new spi operationSuresh Gupta2-1/+31
It is recommended to check either controller is free to take new spi action. The IP_ACC and AHB_ACC bits indicates that the controller is busy in IP or AHB mode respectively. And the BUSY bit indicates that controller is currently busy handling a transaction to an external flash device Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-09-25spi: mxc_spi: support driver modelPeng Fan1-32/+149
Add driver model support for mxc spi driver. Most functions are restructured to be reused by DM and non-DM. Tested on mx6slevk/mx6qsabresd board. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-09-21nds32: spi: Support spi dm driver.rick3-0/+507
Support spi driver and can detect MX25U1635E flash on AE3XX board. Verification: sf probe 0:0 50000000 0 spi_flash_std_probe(sf_Probr.c) spi_flash_probe_slave(sf_Probr.c) SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB NDS32 # sf test 0x100000 0x1000 SPI flash test: 0 erase: 34 ticks, 117 KiB/s 0.936 Mbps 1 check: 15 ticks, 266 KiB/s 2.128 Mbps 2 write: 21 ticks, 190 KiB/s 1.520 Mbps 3 read: 11 ticks, 363 KiB/s 2.904 Mbps Test passed 0 erase: 34 ticks, 117 KiB/s 0.936 Mbps 1 check: 15 ticks, 266 KiB/s 2.128 Mbps 2 write: 21 ticks, 190 KiB/s 1.520 Mbps 3 read: 11 ticks, 363 KiB/s 2.904 Mbps Signed-off-by: rick <rick@andestech.com>
2017-09-18rockchip: spi: Convert to livetreePhilipp Tomsich1-1/+1
Update the Rockchip SPI driver to support a live device tree. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-02x86: ich-spi: Clear atomic preop only when SPI settings are not lockedBin Meng1-1/+2
The atomic preop register can only be written when SPI settings are not locked, otherwise it's read-only. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2017-09-02x86: ich-spi: Remove useless assignment in ich_spi_xfer()Bin Meng1-2/+0
In ich_spi_xfer() when the driver presets control fields, control variable gets assigned twice. Apparently only the last assignment takes effect. Remove the other one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24x86: ich-spi: Move opcode registers configuration to another routineBin Meng1-6/+16
At present the ICH SPI opcode registers configuration is done in the ich_spi_remove() routine, a little bit weird but that's how current. Linux MTD driver works. This changes to move the opcode registers configuration to a separate routine ich_spi_config_opcode() which might be called by U-Boot itself as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24x86: ich-spi: Don't read cached lock statusBin Meng2-8/+23
At present the ICH SPI controller driver reads the controller lock status from its register in the probe routine and saves the lock status to a member of priv. Later the driver uses the cached status from priv to judge whether the controller setting is locked and do different setup. But such logic is only valid when there is only the SPI controller driver that touches the SPI hardware. In fact the lock status change can be trigged outside the driver, eg: during the fsp_notify() call when Intel FSP is used. This changes the driver to read the lock status every time when an SPI transfer is initiated instead of reading the cached one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24x86: ich-spi: Remove unnecessary assignment in ich_init_controller()Bin Meng1-1/+0
There is no need to do another assignment to ich7_spi. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24x86: ich-spi: Remove spi_write_protect_region()Bin Meng1-50/+0
This routine is not called anywhere. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-14Merge branch 'master' of git://git.denx.de/u-boot-rockchipTom Rini1-0/+9
2017-08-13rockchip: spi: enable support for the rk_spi driver for the RK3368Philipp Tomsich1-0/+9
For the RK3368, we can reuse the SPI driver (although we'll have to eventually investigate whether it can be merged with the designware_spi.c driver) also used for the RK3288 and RK3399. This adds the necessary compatible string to support the RK3368. Note that the assumption that GPLL will be clocked at 594MHz is not true for the RK3368, but this will not lead to incorrect functioning (just to a lower-than-expected SPI operating frequency): this has been documented in the driver, so it doesn't cause any headaches when someone next needs to touch the clock code of this driver. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-12OMAP3_SPI: Kconfig: move OMAP3_SPI out of DM_SPI section.Adam Ford1-7/+7
The OMAP3_SPI driver can work with or without DM_SPI. Moving this outside of the #if DM_SPI section allows us to include it on boards that don't support DM_SPI yet. Signed-off-by: Adam Ford <aford173@gmail.com>
2017-08-02Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini1-0/+8
Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: include/configs/ls1046aqds.h include/configs/ls1046ardb.h
2017-08-01spi: fsl_qspi: Pet watchdog even moreAlexander Stein1-0/+8
Pet the watchdog once upon each command call (qspi_xfer) and during each loop iteration in several commands. This fixes a watchdog reset especially during erase command. Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-07-28dm: tegra: spi: Convert to livetreeSimon Glass1-8/+5
Update the tegra114 spi driver to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Beaver, Jetson-TK1 Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28dm: tegra: Convert clock_decode_periph_id() to support livetreeSimon Glass4-4/+4
Adjust this to take a device as a parameter instead of a node. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Beaver, Jetson-TK1 Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-26spi: stm32_qspi: add clk_get_rate() supportPatrice Chotard1-1/+9
Replace proprietary clock_get() by clk_get_rate() The stm32_qspi is now "generic" and can be used by other STM32 SoCs. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-12imx: reorganize IMX code as other SOCsStefano Babic2-2/+2
Change is consistent with other SOCs and it is in preparation for adding SOMs. SOC's related files are moved from cpu/ to mach-imx/<SOC>. This change is also coherent with the structure in kernel. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@nxp.com> CC: Akshay Bhat <akshaybhat@timesys.com> CC: Ken Lin <Ken.Lin@advantech.com.tw> CC: Marek Vasut <marek.vasut@gmail.com> CC: Heiko Schocher <hs@denx.de> CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com> CC: Christian Gmeiner <christian.gmeiner@gmail.com> CC: Stefan Roese <sr@denx.de> CC: Patrick Bruenn <p.bruenn@beckhoff.com> CC: Troy Kisky <troy.kisky@boundarydevices.com> CC: Nikita Kiryanov <nikita@compulab.co.il> CC: Otavio Salvador <otavio@ossystems.com.br> CC: "Eric Bénard" <eric@eukrea.com> CC: Jagan Teki <jagan@amarulasolutions.com> CC: Ye Li <ye.li@nxp.com> CC: Peng Fan <peng.fan@nxp.com> CC: Adrian Alonso <adrian.alonso@nxp.com> CC: Alison Wang <b18965@freescale.com> CC: Tim Harvey <tharvey@gateworks.com> CC: Martin Donnelly <martin.donnelly@ge.com> CC: Marcin Niestroj <m.niestroj@grinn-global.com> CC: Lukasz Majewski <lukma@denx.de> CC: Adam Ford <aford173@gmail.com> CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr> CC: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Soeren Moch <smoch@web.de> CC: Richard Hu <richard.hu@technexion.com> CC: Wig Cheng <wig.cheng@technexion.com> CC: Vanessa Maegima <vanessa.maegima@nxp.com> CC: Max Krummenacher <max.krummenacher@toradex.com> CC: Stefan Agner <stefan.agner@toradex.com> CC: Markus Niebel <Markus.Niebel@tq-group.com> CC: Breno Lima <breno.lima@nxp.com> CC: Francesco Montefoschi <francesco.montefoschi@udoo.org> CC: Jaehoon Chung <jh80.chung@samsung.com> CC: Scott Wood <oss@buserror.net> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Anatolij Gustschin <agust@denx.de> CC: Simon Glass <sjg@chromium.org> CC: "Andrew F. Davis" <afd@ti.com> CC: "Łukasz Majewski" <l.majewski@samsung.com> CC: Patrice Chotard <patrice.chotard@st.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Hans de Goede <hdegoede@redhat.com> CC: Masahiro Yamada <yamada.masahiro@socionext.com> CC: Stephen Warren <swarren@nvidia.com> CC: Andre Przywara <andre.przywara@arm.com> CC: "Álvaro Fernández Rojas" <noltari@gmail.com> CC: York Sun <york.sun@nxp.com> CC: Xiaoliang Yang <xiaoliang.yang@nxp.com> CC: Chen-Yu Tsai <wens@csie.org> CC: George McCollister <george.mccollister@gmail.com> CC: Sven Ebenfeld <sven.ebenfeld@gmail.com> CC: Filip Brozovic <fbrozovic@gmail.com> CC: Petr Kulhavy <brain@jikos.cz> CC: Eric Nelson <eric@nelint.com> CC: Bai Ping <ping.bai@nxp.com> CC: Anson Huang <Anson.Huang@nxp.com> CC: Sanchayan Maity <maitysanchayan@gmail.com> CC: Lokesh Vutla <lokeshvutla@ti.com> CC: Patrick Delaunay <patrick.delaunay@st.com> CC: Gary Bisson <gary.bisson@boundarydevices.com> CC: Alexander Graf <agraf@suse.de> CC: u-boot@lists.denx.de Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-07-11rockchip: spi: dm: convert fdt_get to dev_readPhilipp Tomsich1-8/+7
With the new dev_read functions available, we can convert the rockchip architecture-specific drivers and common drivers used by these devices over to the dev_read family of calls. This change covers the rk_spi.c (SPI driver) used in Rockchip devices. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-08powerpc, 8xx: move SPI driver to drivers/spi/Christophe Leroy3-0/+343
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-06avr32: Retire AVR32 for goodAndy Shevchenko1-2/+2
AVR32 is gone. It's already more than two years for no support in Buildroot, even longer there is no support in GCC (last version is heavily patched 4.2.4). Linux kernel v4.12 got rid of it (and v4.11 didn't build successfully). There is no good point to keep this support in U-Boot either. Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-06-09tegra: spi: Wait a little after setting the clocksSimon Glass1-0/+1
For devices that need a delay between SPI transactions we seem to need an additional delay before the first one if the CPU is running at full speed. Add this, under control of the existing setting. At present it will only be enabled with the Chrome OS EC. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: spi: Convert uclass to livetreeSimon Glass1-17/+14
Update the SPI uclass to support a live device tree. Also adjust spi_slave_ofdata_to_platdata() to accept a device instead of a blob and offset. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: gpio: Add live tree supportSimon Glass1-1/+1
Add support for requesting GPIOs with a live device tree. This involves adjusting the function signature for the legacy function gpio_request_by_name_nodev(), so fix up all callers. Signed-off-by: Simon Glass <sjg@chromium.org> Fixes to stm32f746-disco.c: Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-01dm: core: Replace of_offset with accessor (part 2)Simon Glass1-2/+2
At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: Fix up inclusion of common.hSimon Glass1-0/+2
It is good practice to include common.h as the first header. This ensures that required features like the DECLARE_GLOBAL_DATA_PTR macro, configuration options and common types are available. Fix up some files which currently don't do this. This is necessary because driver model will soon start using global data and configuration in the dm/read.h header file, included via dm.h. The gd->fdt_blob value will be used to access the device tree and CONFIG options will be used to determine whether to support inline functions in the header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: Rename dev_addr..() functionsSimon Glass17-20/+20
These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-18spi: kconfig: add soft spi Kconfig entryPeng Fan1-0/+6
Add the Kconfig entry for SOFT_SPI which uses gpio to simulate the SPI signals. We use it for accessing 74x164 on some i.MX boards. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Jagan Teki <jagan@openedev.com> Cc: Stefano Babic <sbabic@denx.de>
2017-05-17spi: ich: Configure SPI BIOS parameters for Linux upon U-Boot exitStefan Roese2-7/+65
This patch adds a remove function to the Intel ICH SPI driver, that will be called upon U-Boot exit, directly before the OS (Linux) is started. This function takes care of configuring the BIOS registers in the SPI controller (similar to what a "standard" BIOS or coreboot does), so that the Linux MTD device driver is able to correctly read/write to the SPI NOR chip. Without this, the chip is not detected at all. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Jagan Teki <jteki@openedev.com>
2017-05-15omap: spi: Drop CONFIG_OMAP3_SPI_D0_D1_SWAPPED supportTom Rini1-1/+2
This particular quirk is not enabled in any config files today. It does however exist and is handled correctly in device trees and via CONFIG_DM_SPI. So we drop the symbol now and add a comment to indicate that any (new) boards that require this quirk need to enable DM_SPI instead. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-10rockchip: spi: enable support for the rk_spi driver for the RK3399Jakob Unterwurzacher1-0/+1
The existing Rockchip SPI (rk_spi.c) driver also matches the hardware block found in the RK3399. This has been confirmed both with SPI NOR flashes and general SPI transfers on the RK3399-Q7 for SPI1 and SPI5. This change adds the 'rockchip,rk3399-spi' string to its compatible list to allow reuse of the existing driver. X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: spi: rewrite rkspi_set_clk for a more conservative baudrate settingPhilipp Tomsich1-3/+22
The baudrate in rkspi was calculated by using an integer division (which implicitly discarded any fractional result), then rounding to an even number and finally clamping to 0xfffe using a bitwise AND operator. This introduced two issues: 1) for very small baudrates (overflowing the 0xfffe range), the bitwise-AND generates rather random-looking (wildly varying) actual output bitrates 2) for higher baudrates, the calculation tends to 'err towards a higher baudrate' with the actual error increasing as the dividers become very small. E.g., with a 99MHz input clock, a request for a 20MBit baudrate (99/20 = 4.95), a 24.75 MBit would be use (which amounts to a 23.75% error)... for a 34 MBit request this would be an actual outbout of 49.5 Mbit (i.e. a 45% error). This change rewrites the divider selection (i.e. baudrate calculation) by making sure that a) for the normal case: the largest representable baudrate below the requested rate will be chosen; b) for the denormal case (i.e. when the divider can no longer be represented), the lowest representable baudrate is chosen. Even though the denormal case (b) may be of little concern in real world applications (even with a 198MHz input clock, this will only happen at below approx. 3kHz/3kBit), our board-verification team kept complaining. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-05-10rockchip: spi: rk_spi: dynamically select an module input ratePhilipp Tomsich2-8/+37
The original clock/bitrate selection code for the rk_spi driver was a bit limited, as it always selected a 99MHz input clock rate (which would allow for a maximum bitrate of 49.5MBit/s), but returned -EINVAL if a bitrate higher than 48MHz was requested. To give us better control over the bitrate (i.e. add more operating points, especially at "higher" bitrate---such as above 9MBit/s), we try to choose 4x the maximum frequency (clamped to 50MBit) from the DTS instead of 99MHz... for most use-cases this will yield a frequency of 198MHz, but is flexible to go beyond this in future configurations. This also rewrites the check to allow frequencies of up to half the SPI module rate as bitrates and then clamps to whatever the DTS allows as a maximum (board-specific) frequency and does away with the -EINVAL when trying to select a bitrate (for cases that exceeded the hard limit) and instead consistently clamps to the lower of the hard limit, the soft limit for the SPI bus (from the DTS) or the soft limit for the SPI slave device. This replaces "rockchip: spi: rk_spi: select 198MHz input to the SPI module for the RK3399" "rockchip: spi: rk_spi: improve clocking code for the RK3399" from earlier versions of this series. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-05-08stm32f7: use clock driver to enable qspi controller clockVikas Manocha1-1/+15
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-03drivers: spi: Remove duplicate .probe methodSuniel Mahesh1-1/+0
.probe method has been assigned twice when declaring a driver with U_BOOT_DRIVER(). Removed one of them. Here is the last commit which had the duplicate entry: "spi: omap3: Convert to driver model" (sha1: 77b8d04854f486741471ad02b93b473b5b3d72f8) Signed-off-by: Suniel Mahesh <suniel.spartan@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-05-03zynq: spi: Honour the activation / deactivation delayMoritz Fischer1-0/+24
This is not currently implemented. Add support for this so that the Chrome OS EC can be used reliably. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-05-03spi: atmel: check GPIO validity before using cs_gpiosWenyou Yang1-0/+9
Before using the cs_gpio, check if the GPIO is valid or not. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-05Blackfin: RemoveTom Rini3-616/+0
The architecture is currently unmaintained, remove. Cc: Benjamin Matthews <mben12@gmail.com> Cc: Chong Huang <chuang@ucrobotics.com> Cc: Dimitar Penev <dpn@switchfin.org> Cc: Haitao Zhang <hzhang@ucrobotics.com> Cc: I-SYST Micromodule <support@i-syst.com> Cc: M.Hasewinkel (MHA) <info@ssv-embedded.de> Cc: Marek Vasut <marex@denx.de> Cc: Martin Strubel <strubel@section5.ch> Cc: Peter Meerwald <devel@bct-electronic.com> Cc: Sonic Zhang <sonic.adi@gmail.com> Cc: Valentin Yakovenkov <yakovenkov@niistt.ru> Cc: Wojtek Skulski <info@skutek.com> Cc: Wojtek Skulski <skulski@pas.rochester.edu> Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-04dm: core: Add flags parameter to device_remove()Stefan Roese1-2/+2
This patch adds the flags parameter to device_remove() and changes all calls to this function to provide the default value of DM_REMOVE_NORMAL for "normal" device removal. This is in preparation for the driver specific pre-OS (e.g. DMA cancelling) remove support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28spi: fsl_qspi: Add support for single chip selectSuresh Gupta1-1/+4
SOC’s like LS1012A has only one chip select signal for QSPI flash. Avoid scanning other flash. Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
generated by cgit v1.1 at 2024-07-15 16:54:16 +0000