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path: root/drivers/spi
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2021-01-05dm: Use access methods for dev/uclass private dataSimon Glass20-45/+45
Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
2020-12-22dm: spi: Fix spi_free_slave() freed memory writeNiel Fourie1-1/+0
Remove setting slave->dev to NULL after the device_remove() call. The slave pointer points to dev->parent_priv, which has already been freed by device_free(), called from device_remove() in the preceding line. Writing to slave->dev may cause corruption of the dlmalloc free chunk forward pointer of the previously freed chunk. Signed-off-by: Niel Fourie <lusus@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-12-22spi: spi-uclass: Fix spi_claim_bus() speed/mode setup logicOvidiu Panait1-5/+12
Currently, when different spi slaves claim the bus consecutively using spi_claim_bus(), spi_set_speed_mode() will only be executed on the first two calls, leaving the bus in a bad state starting with the third call. This patch drops spi_slave->speed member and adds caching of bus speed/mode in dm_spi_bus struct. It also updates spi_claim_bus() to call spi_set_speed_mode() if either speed or mode is different from what the bus is currently configured for. Current behavior is to only take into account the speed, but not the mode, which seems wrong. Fixes: 60e2809a848 ("dm: spi: Avoid setting the speed with every transfer") Reviewed-by: Simon Glass <sjg@chromium.org> Reported-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reported-by: Moshe, Yaniv <yanivmo@amazon.com> Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2020-12-22test: spi: Add sandbox_spi_get_{speed, mode} interfaceOvidiu Panait1-0/+14
Introduce sandbox_spi_get_{speed, mode} public interface to retrieve the sandbox spi bus internal state. They are meant to be used in sandbox spi testcases. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-12-22spi: sandbox_spi: Implement speed/mode setupOvidiu Panait1-0/+26
Implement sandbox_spi_set_{speed, mode} routines, to be able to keep track of the current bus speed/mode. This will help determine whether the values passed from dm_spi_claim_bus() are valid. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2020-12-22sandbox: test: Add a second SPI slave on sandbox_spi busOvidiu Panait1-2/+2
Place a second spi slave on the sandbox_spi bus, to be used by the spi_claim_bus() testcase we are about to introduce. We need to make sure that jumping between slaves calling spi_claim_bus() sets the bus speed and mode appropriately. Use different max-hz and mode properties for this new slave. Also, update sandbox_spi cs_info call to allow activity on CS0/CS1 and adapt dm_test_spi_find() testcase for this new setup. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-12-22sandbox: spi: Drop unused sandbox_spi_parse_spec functionOvidiu Panait1-16/+0
Commit 1289e96797bf ("sandbox: spi: Drop command-line SPI option") dropped support for specifying SPI devices on the command line, removing the only user of sandbox_spi_parse_spec(). Remove the function too. Fixes: 1289e96797bf ("sandbox: spi: Drop command-line SPI option") Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-12-18dm: Drop the unused arg in uclass_find_device_by_seq()Simon Glass1-2/+2
Now that there is only one sequence number (rather than both requested and assigned ones) we can simplify this function. Also update its caller to simplify the logic. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-18spi: Update for new sequence numbersSimon Glass2-2/+1
Use the new sequence number in all cases. Drop the rockchip case because the sequence number should be 0 anyway, and assigning to the sequence number is not permitted. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-18dm: Avoid accessing seq directlySimon Glass14-22/+22
At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass48-236/+235
Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Update 'auto' declarations to be on one lineSimon Glass1-2/+1
Fix up the code style for those declarations that should now fit onto one line, which is all of them that currently do not. This is needed for dtoc to detect the structs correctly, at present. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass33-65/+65
This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass28-75/+75
Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass47-133/+133
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass51-81/+81
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-30Merge tag 'dm-pull-30oct20' of ↵Tom Rini1-1/+3
https://gitlab.denx.de/u-boot/custodians/u-boot-dm of-platdata and dtoc improvements sandbox SPL tests binman support for compressed sections
2020-10-29x86: apl: Enable SPI flash in TPL with APL_SPI_FLASH_BOOTSimon Glass1-1/+3
At present, enabling CONFIG_APL_SPI_FLASH_BOOT does not build since SPI and SPI flash are not enabled for TPL. Add a condition to fix this and tidy up a build warning in the SPI-flash driver. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-27spi: zynq_qspi: Add function descriptionAshok Reddy Soma1-12/+36
Add function description for zynq_qspi_init_hw and zynq_qspi_chipselect. Fix zqspi to priv in function descriptions. Change the description of priv as pointer to zynq_qspi_priv structure. Fix other function descriptions to kernel-doc style. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27spi: zynq_qspi: Use clk subsystem to get reference qspi clkT Karthik Reddy1-8/+28
Remove fixed reference clk used by plat->frequency and use clk subsystem to get reference clk. As per spi dt bindings "spi-max-frequency" property should be used by the slave devices. This property is read by spi-uclass driver for the slave device. So avoid reading above property from the platform driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27spi: zynq_spi: Use clk subsystem to get reference spi clkT Karthik Reddy1-7/+28
Remove fixed reference clk used by plat->frequency and use clk subsystem to get reference clk. As per spi dt bindings "spi-max-frequency" property should be used by the slave devices. This property is read by spi-uclass driver for the slave device. So avoid reading above property from the platform driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27spi: xilinx_spi: remove unused local variableT Karthik Reddy1-3/+3
Remove unused variable 'count' which is causing warning while compilation. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27spi: xilinx_spi: Remove unused variableMichal Simek1-1/+1
Remove unused variable: drivers/spi/xilinx_spi.c: In function 'xilinx_spi_xfer': drivers/spi/xilinx_spi.c:254:18: warning: unused variable 'timeout' [-Wunused-variable] 254 | u32 reg, count, timeout; | ^~~~~~~ Fixes: 0c0de58f7b30 ("spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() function") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-22spi: Add Qualcomm QUP SPI controller driverRobert Marko3-0/+814
This patch adds support for the Qualcomm QUP SPI controller that is commonly found in most of Qualcomm SoC-s. Driver currently supports v1.1.1, v2.1.1 and v2.2.1 HW. FIFO and Block modes are supported, no support for DMA mode is planned. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-20spi: renesas_rpc_spi: Add R-Car Gen3 and RZ/G2 fallback compatibility stringBiju Das1-1/+2
Add fallback compatibility string for R-Car Gen3 and RZ/G2. Also sorted the compatible string as per SoC ID. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-16Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini1-1/+4
- Fix Octeon SPI driver for Octeon TX2 - Fix and enhance Octeon watchdog driver - Misc minor enhancements to Octeon TX/TX2
2020-10-16spi: fsl_qspi: Include device_compat.hSean Anderson1-4/+5
Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-16spi: nxp_fspi: Include device_compat.hSean Anderson1-3/+4
Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-16spi: octeon_spi: Use a fixed 100MHz input clock on Octeon TX2Stefan Roese1-1/+4
Octeon TX2 sets the TB100_EN bit in the config register. We need to use a fixed 100MHz clock for this as well to work properly. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Jagan Teki <jagan@amarulasolutions.com>
2020-10-14Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini1-6/+35
- Octeon TX: Add NAND driver (Suneel) - Octeon TX: Add NIC driver driver (Suneel) - Octeon TX2: Add NIC driver driver (Suneel) - Armada 8040: Add iEi Puzzle-M80 board support (Luka) - Armada A37xx SPI: Add support for CS-GPIO (George) - Espressobin: Use Linux model/compatible strings (Andre) - Espressobin: Add armada-3720-espressobin-emmc.dts from Linux (Andre) - Armada A37xx: Small cleanup of config header (Pali)
2020-10-14treewide: Fix wrong CONFIG_IS_ENABLED() handlingAlper Nebi Yasak1-5/+5
CONFIG_IS_ENABLED() takes the kconfig name without the CONFIG_ prefix, e.g. CONFIG_IS_ENABLED(CLK) for CONFIG_CLK. Some of these were being fixed every now and then, see: commit 71ba2cb0d678 ("board: stm32mp1: correct CONFIG_IS_ENABLED usage for LED") commit a5ada25e4213 ("rockchip: clk: fix wrong CONFIG_IS_ENABLED handling") commit 5daf6e56d36c ("common: console: Fix duplicated CONFIG in silent env callback") commit 48bfc31b6484 ("MIPS: bootm: Fix broken boot_env_legacy codepath") Fix all files found by `git grep "CONFIG_IS_ENABLED(CONFIG"` by running ':%s/CONFIG_IS_ENABLED(CONFIG_\(\w+\))/CONFIG_IS_ENABLED(\1)/g' in vim. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-14spi: mvebu_a3700_spi: add support for cs-gpiosGeorge Hilliard1-6/+35
The device tree has a way to specify GPIO lines as chip selects. From the binding docs: So if for example the controller has 2 CS lines, and the cs-gpios property looks like this: cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>; Then it should be configured so that num_chipselect = 4 with the following mapping: cs0 : &gpio1 0 0 cs1 : native cs2 : &gpio1 1 0 cs3 : &gpio1 2 0 Add support for this, while retaining backward-compatibility with existing device trees; the driver will preserve existing behavior if a cs-gpios list is not given, or if a particular line is specified as <0> (native). This implementation is inspired by similar implementations in neighboring drivers for other platforms: atmega, mxc, etc. Signed-off-by: George Hilliard <ghilliar@amazon.com> Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-05Merge branch 'next'Tom Rini5-90/+34
Bring in the assorted changes that have been staged in the 'next' branch prior to release. Signed-off-by: Tom Rini <trini@konsulko.com>
2020-09-30spi: zynqmp_gqspi: Fix not calling dev_err with a deviceSean Anderson1-3/+3
Use `bus` instead of `dev`. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30spi: sunxi: Fix not calling dev_err with a deviceSean Anderson1-3/+3
Use `bus` and not `dev`. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-24Merge tag 'xilinx-for-v2021.01' of ↵Tom Rini1-3/+0
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.01 arm64: - Support for bigger U-Boot images compiled with PIE microblaze: - Extend support for LE/BE systems zynqmp: - Refactor silicon ID detection code with using firmware interface - Add support for saving variables based on bootmode zynqmp-r5: - Fix MPU mapping and defconfig setting. xilinx: - Minor driver changes: names alignment - Enable UBIFS - Minor DT and macros fixes - Fix boot with appended DT - Fix distro boot cmd: - pxe: Add fixing for platforms with manual relocation support clk: - fixed_rate: Add DM flag to support early boot on r5 fpga: - zynqmppl: Use only firmware interface and enable SPL build serial: - uartlite: Enable for ARM systems and support endians mmc: - zynq: Fix indentation net: - gem: Support for multiple phys - emac: Fix 64bit support and enable it for arm64 kconfig: - Setup default values for Xilinx platforms - Fix dependecies for Xilinx drivers - Source board Kconfig only when platform is enabled - Fix FPGA Kconfig entry with SPL - Change some defconfig values bindings: - Add binding doc for vsc8531
2020-09-23xilinx: kconfig: Change Kconfig dependencies for Xilinx driversMichal Simek1-3/+0
Zynq/ZynqMP/Versal IPs should be possible to called also from Microblaze in PL and vice versa. That's why change dependencies and do not limit enabling just for some platforms. This is follow up patch based on commit 664e16ce99a0 ("xilinx: kconfig: Change Kconfig dependencies for Xilinx drivers"). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-22spi: mpc8xxx_spi.c: fix cs activate/deactivateRasmus Villemoes1-4/+2
Somewhere between v2020.04 and v2020.07 the mpc8xxx_spi driver broke, I'm guessing due to this hunk @@ -559,6 +560,8 @@ int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags) if (ret) return ret; + /* combine the requested flags (for IN/OUT) and the descriptor flags */ + flags |= desc->flags; ret = _dm_gpio_set_dir_flags(desc, flags); from commit 695e5fd5469a ("gpio: update dir_flags management"). But the blame is mostly on the driver itself which seems rather confused: The chip select gpios are requested with GPIOD_ACTIVE_LOW, but then in each activate/deactivate, dm_gpio_set_dir_flags() is called with merely GPIOD_IS_OUT, and then the driver call set_value(0) for activate. That used to work, but with the above hunk, the ACTIVE_LOW setting from the request becomes persistent, so the gpio driver ends up being asked to set the value to 1 in mpc8xxx_spi_cs_activate(). So drop the dm_gpio_set_dir_flags() calls in the activate/deactivate functions, and use a value of 1 to mean "logically enabled". Ideally, I think we should also drop the GPIOD_ACTIVE_LOW from the request and make it up to the list of gpio cs in DT to indicate whether that CS is enabled when driven low (as is of course usually the case), but that requires changing arch/powerpc/dts/gdsys/gazerbeam-base.dtsi among others, and I don't have that hardware to test on. I have, however, tested our own (mpc8309-based) hardware with this change, and I have also tested that removing the GPIOD_ACTIVE_LOW from the request and updating our DT as - gpios = <&spisel 0 0>; + gpios = <&spisel 0 GPIO_ACTIVE_LOW>; still works. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-09-15spi: omap3_spi: Read platform data in ofdata_to_platdata()Faiz Abbas1-11/+26
Add an ofdata_to_platdata() callback to access dts in U-boot and access all platform data in it. This prepares the driver for supporting both device tree as well as static platform data structures in SPL. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-09-15arm: mach-omap2: am33xx: Add device structure for spiFaiz Abbas1-69/+1
Add platform data and a device structure for the spi device present on am335x-icev2. This requires moving all omap3_spi platform data structures and symbols to an omap3_spi.h so that the board file can access them. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-09-15spi: spi-uclass: Block dm_scan_fdt_dev with OF_CONTROL to prevent build failuresFaiz Abbas1-1/+1
There are devices which don't use OF_CONTROL or OF_PLATDATA but instead rely on statically defined platdata. Block dm_scan_fdt_dev() with both configs to avoid build failures under this condition. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-08-22treewide: convert devfdt_get_addr_ptr() to dev_read_addr_ptr()Masahiro Yamada1-1/+1
When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To help this tedious work, this commit converts devfdt_get_addr_ptr() to dev_read_addr_ptr() by coccinelle. I also removed redundant casts because dev_read_addr_ptr() returns an opaque pointer. To generate this commit, I ran the following semantic patch excluding include/dm/. <smpl> @@ type T; expression dev; @@ -(T *)devfdt_get_addr_ptr(dev) +dev_read_addr_ptr(dev) @@ expression dev; @@ -devfdt_get_addr_ptr(dev) +dev_read_addr_ptr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-04Merge tag 'mips-pull-2020-08-03' of ↵Tom Rini3-0/+622
https://gitlab.denx.de/u-boot/custodians/u-boot-mips - doc: fix qemu-mips build instructions - MIPS: add GPIO, CLK and SPI drivers for Octeon MIPS64
2020-08-03spi: Drop duplicate dm.h inclusionSimon Glass1-1/+0
We only need to include this header once. Drop the duplicate. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03mtd: spi-mem: Drop dm.h header fileSimon Glass3-1/+9
This header file should not be included in other header files. Remove it and use a forward declaration instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03drivers: spi: Add SPI controller driver for OcteonSuneel Garapati3-0/+622
Adds support for SPI controllers found on Octeon II/III and Octeon TX TX2 SoC platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-07-28drivers: avoid using aliases on drivers when OF_PLATDATA is enabledWalter Lozano1-8/+2
After latest improvements on OF_PLATDATA struct names are generated based on driver name instead of compatible strings. With this in mind, using aliases in drivers are not longer needed. This patch removes code that tried to handle these kind of aliases to improve readability. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-27Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini1-1/+53
- Bug fixes and updates on ls2088a,ls1028a, ls1046a, ls1043a, ls1012a - lx2-watchdog support - layerscape: pci-endpoint support, spin table relocation fixes and cleanups - fsl-crypto: RNG support and bug fixes
2020-07-27fsl_dspi: Introduce DT bindings for CS-SCK and SCK-CS delaysVladimir Oltean1-1/+53
Communication with some SPI slaves just won't cut it if these delays (before the beginning, and after the end of a transfer) are not added to the Chip Select signal. These are a straight copy from Linux: Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt drivers/spi/spi-fsl-dspi.c Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-25treewide: convert devfdt_get_addr() to dev_read_addr()Masahiro Yamada13-14/+14
When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
generated by cgit v1.1 at 2024-07-14 06:35:51 +0000