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2020-12-13dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass6-27/+22
Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass10-20/+20
This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass9-30/+30
Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass10-10/+10
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass20-28/+28
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-30Merge tag 'u-boot-rockchip-20201031' of ↵Tom Rini2-0/+29
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - New PX30 board: Engicam PX30.Core; - Fix USB HID support for rock960; - Remove host endianness dependency for rockchip mkimage; - dts update for rk3288-tinker; - Enable console MUX for some ROCKPi boards; - Add config-based ddr selection for px30;
2020-10-30ram: rockchip: px30: add a config-based ddr selectionHeiko Stuebner2-0/+29
The SRAM on the PX30 is not big enough to hold multiple DDR configs so it needs to be selected during build. So far simply the DDR3 config was always selected and getting DDR4 or LPDDR2/3 initialized would require a code modification. So add Kconfig options similar to RK3399 to allow selecting the DDR4 and LPDDR2/3 options instead, while DDR3 stays the default as before. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-22common: rename getc() to getchar()Heinrich Schuchardt1-1/+1
The sandbox is built with the SDL2 library with invokes the X11 library which in turn calls getc(). But getc() in glibc is defined as int getc(FILE *) This does not match our definition. int getc(void) The sandbox crashes when called with parameter -l. Rename our library symbol getc() to getchar(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-15ram: imxrt: Include device_compat.hSean Anderson1-0/+1
Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-08ram: add ddr4 dual x8 configurationDylan Hung3-1/+12
the aspeed ddr sdram controller needs to know if the memory chip mounted on the board is dual x8 die or not. Or it may get the wrong size of the memory space. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-10-08ram: move aspeed ram driver into drivers/ directoryDylan Hung3-0/+443
to improve the maintainability. It is more easier to modify and add configurations of the driver in the centralized ram driver directory. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-10-07ram: octeon: Add MIPS Octeon3 DDR4 support (part 3/3)Aaron Williams5-0/+435
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot repository. It currently supports DDR4 on Octeon 3. It can be later extended to support also DDR3 and Octeon 2 platforms. Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile integration. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07ram: octeon: Add MIPS Octeon3 DDR4 support (part 2/3)Aaron Williams1-0/+11030
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot repository. It currently supports DDR4 on Octeon 3. It can be later extended to support also DDR3 and Octeon 2 platforms. Part 2 includes the very complex Octeon 3 DDR4 configuration Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07ram: octeon: Add MIPS Octeon3 DDR4 support (part 1/3)Aaron Williams1-0/+2728
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot repository. It currently supports DDR4 on Octeon 3. It can be later extended to support also DDR3 and Octeon 2 platforms. Part 1 adds the base U-Boot RAM driver, which will be instantiated by the DT based probing. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2020-09-30ram: sifive: Remove regmap dependencyBin Meng1-9/+3
The usage of regmap API in the SiFive RAM driver is not correct. The reg address should be obtained via dev_read_addr_index() API. Signed-off-by: Bin Meng <bin.meng@windriver.com>
2020-09-30ram: sifive: Check return value on clk_enable()Bin Meng1-0/+5
The return value should be checked otherwise it's useless to assign the return value to 'ret'. Signed-off-by: Bin Meng <bin.meng@windriver.com>
2020-08-25ram: sifive: Fix compiler warnings for 32-bitBin Meng1-2/+2
priv->info.size is of type 'size_t' but the length modifier is l. Fix this by casting priv->info.size. Note 'z' cannot be used as the modifier as SPL does not support that. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
2020-08-11ram: k3-j721e: Relax version checks for memory controllerLokesh Vutla1-15/+1
k3-j721e ddr driver sanity checks for product id and version number. Version number gets changed for every minor update in the IP. So discard the version check and just sanity check for product id. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-08-03ti: am654: Drop duplicate dm.h inclusionSimon Glass1-1/+0
We only need to include this header once. Drop the duplicate. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-24ram: sifive: Avoid using hardcoded ram base and sizeBin Meng1-15/+15
At present the SiFive FU540 RAM driver uses hard-coded memory base address and size to initialize the DDR controller. This may not be true when this driver is used on another board based on FU540. Update the driver to read the memory information from DT and use that during the initialization. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Leo Liang <ycliang@andestech.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-22rockchip: ram: fix debug funcfion define when RAM_ROCKCHIP_DEBUG not setKever Yang1-0/+13
The empty function define should not be in the header file, or else the build will error with function multi definition after CONFIG_RAM_ROCKCHIP_DEBUG is disabled. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22ram: rk3399: Mark existing prints via RAM_ROCKCHIP_DEBUGJagan Teki1-4/+8
Right now all these debug statements are printing on the console to make sure proper dram initialization happens.   Mark them into RAM_ROCKCHIP_DEBUG would be more meaningful and work like before since the RAM_ROCKCHIP_DEBUG is by default yet. No functionality changes. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22ram: rk3399: Drop debug stride in driverJagan Teki1-25/+0
stride debug is already present in sdram_common.c via RAM_ROCKCHIP_DEBUG. So, drop the redundant debug stride code in rk3399 driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-09dtoc: extend dtoc to use struct driver_info when linking nodesWalter Lozano1-1/+1
In the current implementation, when dtoc parses a dtb to generate a struct platdata it converts the information related to linked nodes as pointers to struct platdata of destination nodes. By doing this, it makes difficult to get pointer to udevices created based on these information. This patch extends dtoc to use struct driver_info when populating information about linked nodes, which makes it easier to later get the devices created. In this context, reimplement functions like clk_get_by_index_platdata() which made use of the previous approach. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-09drivers: rename drivers to match compatible stringWalter Lozano4-4/+4
When using OF_PLATDATA, the bind process between devices and drivers is performed trying to match compatible string with driver names. However driver names are not strictly defined, and also there are different names used when declaring a driver with U_BOOT_DRIVER, the name of the symbol used in the linker list and the used in the struct driver_info. In order to make things a bit more clear, rename the drivers names. This will also help for further OF_PLATDATA improvements, such as checking for valid driver names. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> Add a fix for sandbox of-platdata to avoid using an invalid ANSI colour: Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-07ram: stm32mp1: add size and addr parameter to test allPatrick Delaunay1-3/+44
Add size and addr parameter to test "All" to override the default value (4kB and STM32_DDR_BASE) used in tests with these optional parameters: [size] or [addr]. When other optional parameters are present before [addr], they are replaced by default value: - [loop] = "1" - [pattern] = "-" (new: force default pattern) Example to use: DDR>test 0 1 0x20000 DDR>test 0 1 0x1000000 0xD0000000 Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-07-07ram: stm32mp1: use the DDR size by default in the test addressBusPatrick Delaunay1-1/+2
The test 4 = "AddressBus [size] [addr]" without parameter detects alias for any address bit only when: - size = real size of DDR - addr = start of DDR = 0xC0000000 These value must be the default value when parameters are absent. This patch sets bufsize to STM32_DDR_SIZE and get_bufsize() selects the correct value for bufsize when this parameter is absent = full size of the DDDR On EV1 board : DDR> test 4 running at 0xC0000000 length 0x40000000 On DK2 board DDR> test 4 running at 0xC0000000 length 0x20000000 Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-07-07ram: stm32mp1: add parameter addr in test FrequencySelectivePatternPatrick Delaunay1-6/+7
Add a parameter addr in test FrequencySelectivePattern to select the base address used to execute the tests. Default value (when the parameter is absent) is STM32_DDR_BASE, selected in get_addr() function. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-07-07ram: stm32mp1: protect minimum value in get_bufsizePatrick Delaunay1-18/+19
Add protection on minimum value for result of get_bufsize and check the alignment of buffer size: only multiple min_size is allowed; only 4 bytes alignment was checked previously (value & 0x3). For example the "Random" test raises an issue when size is not 8 bytes aligned because address for buffer = address + size / 2 is not word aligned. This patch avoid test error for unsupported size value. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-06-04sifive: fu540: add ddr driverPragnesh Patel5-0/+432
Add driver for fu540 to support ddr initialization in SPL. This driver is based on FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass8-0/+8
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop linux/delay.h from common headerSimon Glass14-0/+14
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop log.h from common headerSimon Glass17-0/+17
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18command: Remove the cmd_tbl_t typedefSimon Glass1-5/+6
We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop init.h from common headerSimon Glass8-0/+8
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop net.h from common headerSimon Glass2-0/+2
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-14ram: stm32mp1: Add support for multiple configsMarek Vasut1-5/+28
Add support for multiple DRAM configuration subnodes, while retaining the support for a single flat DRAM configuration node. This is useful on systems which can be manufactured in multiple configurations and where the DRAM configuration can be determined at runtime. The code is augmented by a function which can be overridden on board level, allowing a match on the configuration node name, very much like the fitImage configuration node name matching works. The default match is on the single top-level DRAM configuration, if matching on subnodes is required, then this board_stm32mp1_ddr_config_name_match() must be overridden. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-15configs: stm32mp1: replace STM32MP1_TRUSTED by TFABOOTPatrick Delaunay1-1/+1
Activate ARCH_SUPPORT_TFABOOT and replace the arch stm32mp specific config CONFIG_STM32MP1_TRUSTED by the generic CONFIG_TFABOOT introduced by the commit 535d76a12150 ("armv8: layerscape: Add TFABOOT support"). This config CONFIG_TFABOOT is activated for the trusted boot chain, when U-Boot is loaded by TF-A. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: the property st, phy-cal becomes optionalPatrick Delaunay4-16/+51
This parameter "st,phy-cal" becomes optional and when it is absent the built-in PHY calibration is done. It is the case in the helper dtsi file "stm32mp15-ddr.dtsi" except if DDR_PHY_CAL_SKIP is defined. This patch also impact the ddr interactive mode - the registers of the param 'phy.cal' are initialized to 0 when "st,phy-cal" is not present in device tree (default behavior when DDR_PHY_CAL_SKIP is not activated) - the info 'cal' field can be use to change the calibration behavior - cal=1 => use param phy.cal to initialize the PHY, built-in training is skipped - cal=0 => param phy.cal is absent, built-in training is used (default) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: reduce delay after BIST reset for tuningPatrick Delaunay1-1/+1
Reduce the delay after BIST delay, from 1ms to 10us which is enough accoriding datasheet. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1_ddr: fix self refresh disable during DQS trainingPatrick Delaunay2-1/+5
DDRCTRL_PWRCTL.SELFREF_EN needs to be reset before DQS training step, not to enter in self refresh mode during the execution of this phase. Depending on settings, it can be set after the DQS training. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: update BIST config for tuningPatrick Delaunay1-9/+142
Update the BIST config to compute the real use mask for the real bank, row and col of the used DDR. The values are get from addrmap register value. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: tuning: deactivate derating during BIST testPatrick Delaunay1-0/+15
The derating (timing parameter derating using MR4 read value) can't be activated during BIST test, as the MR4 read answer will be not understood by BIST (BISTGSR.BDONE bit stay at 0, BISTWCSR.DXWCNT = 0x206 instead of BISTWCR.BWCNT = 0x200). This patch only impacts the tuning on LPDDR2/LPDDR3, if derateen.derate_enable = 1. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: tuning: add timeout for polling BISTGSR.BDDONEPatrick Delaunay1-20/+25
Avoid to block the tuning procedure on BIST error (not finished BIST procedure) by adding a 1000us timeout on the polling of BISTGSR.BDDONE executed to detect the end of BIST. The normal duration of the BIST test is around 5us. This patch also cleanup comments. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: don't display the prompt two timesPatrick Delaunay1-3/+1
Remove one "DDR>" display on command - next - step - go Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: display result for software read DQS gatingPatrick Delaunay1-4/+6
Display result information for software read DQS gating, the tuning 0 which be used by CubeMX DDR tuning tools. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: increase vdd2_ddr: buck2 for 32bits LPDDRPatrick Delaunay1-5/+25
Need to increase the LPDDR2/LPDDR3 the voltage vdd2_ddr: buck2 form 1.2V to 1.25V for 32bits configuration. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-02-13ram: rockchip: Fix Kconfig dependency for RAM_ROCKCHIP_DEBUGMichal Simek1-0/+1
There is no reason to show RAM_ROCKCHIP_DEBUG entry in other .config files as I see it for Xilinx ZynqMP. \# CONFIG_U_QE is not set \# CONFIG_RAM is not set CONFIG_RAM_ROCKCHIP_DEBUG=y Add missing dependency on RAM_ROCKCHIP driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-02-05dm: core: Drop the inclusion of linux/compat.h in dm.hSimon Glass1-0/+1
Most files don't need this header and it pulls in quite of lots of stuff, malloc() in particular. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: core: Create a new header file for 'compat' featuresSimon Glass3-0/+3
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
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