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path: root/drivers/pinctrl/rockchip
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2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass11-11/+11
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-09drivers: rename drivers to match compatible stringWalter Lozano4-4/+4
When using OF_PLATDATA, the bind process between devices and drivers is performed trying to match compatible string with driver names. However driver names are not strictly defined, and also there are different names used when declaring a driver with U_BOOT_DRIVER, the name of the symbol used in the linker list and the used in the struct driver_info. In order to make things a bit more clear, rename the drivers names. This will also help for further OF_PLATDATA improvements, such as checking for valid driver names. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> Add a fix for sandbox of-platdata to avoid using an invalid ANSI colour: Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass11-0/+11
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop log.h from common headerSimon Glass10-0/+10
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop image.h from common headerSimon Glass1-0/+1
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2019-12-06pinctrl: rockchip: Add pinctrl support for rk3308David Wu4-1/+468
An iomux register contains 8 pins, each of which is represented by 2 bits, but the register offset is 0x8. For example, GRF_GPIO0A_IOMUX offset is 0x0, but GRF_GPIO0B_IOMUX offset is 0x8, the offset 0x4 is reserved. So add a type IOMUX_8WIDTH_2BIT to calculate offset. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17pinctrl: rockchip: add px30 pinctrl driverDavid Wu2-0/+369
Add the necessary glue code to allow pinctrl setting on px30 socs. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Also move common set_schmitter func into per Soc fileDavid Wu4-21/+37
Only some Soc need Schmitter feature, so move the implementation into their own files. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Clean the unused type and labelDavid Wu10-30/+0
As the mux/pull/drive feature implement at own file, the type and label are not necessary. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' pullDavid Wu1-2/+9
RK3288 pmu_gpio0 pull setting have no higher 16 writing corresponding bits, need to read before write the register. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Split the common set_pull() func into per SocDavid Wu11-112/+275
As the common set_mux func(), implement the feature at the own file for each Soc. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' drive strengthDavid Wu1-2/+9
RK3288 pmu_gpio0 drive strength setting have no higher 16 writing corresponding bits, need to read before write the register. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Split the common set_drive() func into per SocDavid Wu8-100/+224
As the common set_mux func(), implement the feature at the own file for each Soc. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' iomuxDavid Wu1-1/+9
RK3288 pmu_gpio0 iomux setting have no higher 16 writing corresponding bits, need to read before write the register. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Split the common set_mux() into per SocDavid Wu11-32/+297
Such as rk3288's pins of pmu_gpio0 are a special feature, which have no higher 16 writing corresponding bits, use common set_mux() func would introduce more code, so implement their set_mux() in each Soc's own file to reduce the size of code. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Remove redundant spacesDavid Wu7-63/+63
Some files have the redundant spaces, remove them. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Add pull-pin-default param and remove unused paramDavid Wu1-2/+1
Some Socs use the pull-pin-default config param, need to add it. And input-enable/disable config params are not necessary, remove it. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08Revert "pinctrl: rockchip: Add 32bit writing function for rk3288 gpio0 pinctrl"Kever Yang3-76/+13
This reverts commit 502980914b2d6f9ee85a823aa3ef9ead76c0b7f2. This is a superseded version, revert this to apply new patch set. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-03-29pinctrl: rockchip: Add 32bit writing function for rk3288 gpio0 pinctrlDavid Wu3-13/+76
There are no higher 16 writing corresponding bits for pmu_gpio0's iomux/drive/pull at rk3288, need to read the value from register firstly. Add the flag to distinguish it from normal registers. Signed-off-by: David Wu <david.wu@rock-chips.com>
2019-02-01pinctrl: rockchip: Clean the unused rockchip pinctrl driversDavid Wu9-6387/+0
If we used the pinctrl-rockchip driver, these code is not needed, so remove them. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01pinctrl: rockchip: Add common rockchip pinctrl driverDavid Wu13-9/+2530
Use this driver to fit all Rockchip SOCs and to support the desired pinctrl configuration via DTS. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01rockchip: rk3288: Add i2s pinctrl and clock supportSimon Glass1-0/+14
Add support for setting pinctrl and clock for I2S on rk3288. This allows the sound driver to operate. These settings were created by rkmux.py Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-06rockchip: rk3399: fix missing braces in full pinctrlPhilipp Tomsich1-2/+3
Braces around the error-case for rk3399_pinctrl_set_pin_pupd lead to an unconditional (and unintended) return from the function without it ever setting pin-configurations. Fix it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-02rockchip: rk3399: Add Kconfig option for full pinctrl driverChristoph Muellner1-0/+9
This patch adds a Kconfig option to enable the full pinctrl driver for the RK3399. This flag needs to be enabed in order to get the features of the full pinctrl driver compiled in (i.e. a .set_state() callback). Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-02rockchip: rk3399: Add improved pinctrl driver.Christoph Muellner1-0/+227
The current pinctrl driver for the RK3399 has a range of qulity issues. E.g. it only implements the .set_state_simple() callback, it does not parse the available pinctrl information from the DTS (instead uses hardcoded values), is not flexible enough to cover devices without 'interrupt' field in the DTS (e.g. PWM), is not written generic enough to make code reusable among other rockchip SoCs... This patch addresses these issues by reimplementing the whole driver from scratch using the .set_state() callback. The new implementation covers all featurese of the old code (i.e. it supports pinmuxing and pullup/pulldown configuration). This patch has been tested on a RK3399-Q7 SoM (Puma). Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini10-20/+10
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTRTom Rini5-10/+0
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-03-28rockchip: pinctrl: rk3188: Move the iomux definitions into pinctrl-driverAlexander Kochetkov1-0/+380
Clean the iomux definitions at grf_rk3188.h, and move them into pinctrl-driver for resolving the compiling error of redefinition. Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-28rockchip: pinctrl: rk3036: Move the iomux definitions into pinctrl-driverAlexander Kochetkov1-0/+410
Clean the iomux definitions at grf_rk3036.h, and move them into pinctrl-driver for resolving the compiling error of redefinition. Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-28rockchip: pinctrl: rk3399: add support for I2C[123467]Philipp Tomsich1-6/+55
This adds support for the (to date unsupported) I2C controllers 1~4 and 6~7 (i.e. now all controllers except I2C5, which is not accessible on the RK3399-Q7, are supported by pinctrl). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28rockchip: pinctrl: Add rk322x gmac pinctrl supportDavid Wu1-0/+148
Set gmac pins iomux and rgmii tx pins to 12ma drive-strength, clean others to 2ma. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28rockchip: pinctrl: rk322x: Move the iomux definitions into pinctrl-driverDavid Wu1-0/+453
Clean the iomux definitions at grf_rk322x.h, and move them into pinctrl-driver for resolving the compiling error of redefinition. After that, define the uart2 iomux at rk322x-board file. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28rockchip: pinctrl: Add rk3328 gmac pinctrl supportDavid Wu1-0/+275
Need to set gmac m1 pins iomux, gmac m0 tx pins, select bit2 and bit10 at com iomux register. After that, set rgmii m1 tx pins to 12ma drive-strength, and clean others to 2ma. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28rockchip: pinctrl: rk3328: Move the iomux definitions into pinctrl-driverDavid Wu1-0/+113
Clean the iomux definitions at grf_rk3328.h, and move them into pinctrl-driver for resolving the compiling error of redefinition. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28rockchip: pinctrl: rv1108: Move the iomux definitions into pinctrl-driverDavid Wu1-0/+399
If we include both the rk3288_grf.h and rv1108_grf.h, it will cause the conflicts of redefinition. Clean the iomux definitions at grf_rv1108.h, and move them into pinctrl-driver. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: rk3128: add pinctrl driverKever Yang2-2/+189
Add rk3128 pinctrl driver and grf/iomux structure definition. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-26rockchip: pinctrl: rk3399: add support for I2C8Philipp Tomsich1-0/+19
The RK3399 has a total of 9 I2C controllers. To support these, the enum in periph.h is extended and the mapping from the IRQ numbers to the peripheral-ids is extended to ensure that pinctrl requests are passed through to the function configuring the I2C pins. For I2C8, the pinctrl is implemented and tested (on a RK3399-Q7) using communication with the FAN53555 connected on I2C8. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-10-01rockchip: pinctrl: rk3368: add pinctrl for SDMMC0Philipp Tomsich1-5/+34
Apparently, our earlier assumption that the BROM will always set up the iomux for SDcard communication does not always hold true: when booting U-Boot from the on-module (on the RK3368-uQ7) eMMC, the SDcard pins are not set up and need to be configured by the pinctrl driver to allow SD card access. This change implements support for setting up the SDMMC pins in pinctrl for the RK3368. Reported-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18rockchip: pinctrl: rk3368: Convert to livetreePhilipp Tomsich1-2/+1
Update the pinctrl driver for the RK3368 to support a live device tree. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18rockchip: rk322x: pinctrl: fix IO MASK error on sdcard pinKever Yang1-1/+1
Fix the IOMUX setting for SDcard CMD pin at the same time. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18rockchip: rk322x: pinctrl: using compatible name same with dtsKever Yang1-3/+3
The dts from kernel is using rk3228-pinctrl as compatible name, need to sync with it to make the driver work. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-13rockchip: pinctrl: rk3368: add SPI supportPhilipp Tomsich1-0/+118
To implement pinctrl support for the RK3368, we need to add the bit-definitions to configure the IOMUX and tie these into the pinctrl framework. This also adds the mapping from the IRQ# back onto the periheral id for the SPI devices. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: pinctrl: rk3368: move IOMUX bit-definitions to pinctrl driverPhilipp Tomsich1-0/+366
There is no real reason to keep the bit-definitions for the IOMUX in the grf header file (which defines the register layout of the GRF block): these should only be used by our pinctrl driver (with the possible exception of early debug-init code in TPL/SPL). This moves the relevant definitions from the grf_rk3368.h header into the pinctrl driver pinctrl_rk3368.c. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: pinctrl: rk3368: add support for configuring the MMC pinsPhilipp Tomsich1-0/+48
The RK3368 has two SD/MMC controllers that can be used from U-Boot both during SPL and for booting an OS from the full bootloader stage. While both are configured to (mostly) sensible settings from the BROM, additional configuration for the MMC controller is needed to configure it to 8bit mode. This adds pinctrl support for the MMC controller. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: pinctrl: rk3368: add GMAC (RGMII only) supportPhilipp Tomsich1-0/+36
To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this point), we need support for additional pin-configuration. This commit adds the pinctrl support for GMAC in RGMII mode: * adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID * configures the RGMII pins Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13rockchip: rk3368: grf: use shifted-constantsPhilipp Tomsich1-6/+3
The RK3368 GRF header was still defines with a shifted-mask but with non-shifted function selectors for the IOMUX defines. As the RK3368 support is still fresh enough to allow a quick change, we do this now before having more code use this. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: rk3288: Add support for drive-strength in PINCTRLRomain Perier1-1/+9
Currently, drive-strenght to 12ma are described and supposed to be used on RK3288. However, the pinctrl driver for this SoC only handles muxing and pull up/pull down via PU/PD control registers. So complex IPs like GMAC are working in normal ethernet 100mbps, but not at 1gbps typically. This commit adds support for handling drive-strength of 12ma, when it's defined in the DT. Signed-off-by: Romain Perier <romain.perier@collabora.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: rk3288: Revert MAC_TXCLK in pinctrl for GMACRomain Perier1-0/+4
This reverts TXCLK toggling that was accidently dropped while reworking commit 2454b719fb87 ("rockchip: rk3288: Add pinctrl support for the gmac ethernet interface"). So the TX clock is enabled and we can use GMAC_ROCKCHIP in 1Gbps when basic PINCTRL support is enabled (!PINTRL_FULL). Fixes: 2454b719fb87 ("rockchip: rk3288: Add pinctrl support for the...") Signed-off-by: Romain Perier <romain.perier@collabora.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: rk3288: Remove phy reset GPIO pull upRomain Perier1-3/+1
We should not handle this pin explicitly from pinctrl. GMAC driver takes care of it by using a "reset-gpio" in the DT. This commit removes pull up for GPIO4B0. Fixes: 2454b719fb87 ("rockchip: rk3288: Add pinctrl support for the...") Signed-off-by: Romain Perier <romain.perier@collabora.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: rk3288: Add pinctrl support for the gmac ethernet interfaceSjoerd Simons1-0/+118
Add support for the gmac ethernet interface to pinctrl. This hardcodes the setup to match that of the firefly and Radxa Rock2 boards, using the RGMII phy mode for gmac interface and GPIO4B0 as the phy reset GPIO. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Romain Perier <romain.perier@collabora.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
generated by cgit v1.1 at 2024-08-14 00:52:17 +0000