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2023-04-28phy: sun4i-usb: Do not drive VBUS with external VBUS presentSamuel Holland1-0/+6
It is possible to use host-side USB with externally-provided VBUS. For example, some USB OTG cables have an extra power input which powers both the board and the USB peripheral. To support this setup, skip enabling the VBUS switch/regulator if VBUS voltage is already present. This behavior matches the Linux PHY driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-24arm: mach-k3: Remove empty sys_proto.h includeAndrew Davis1-1/+0
This header file is now empty, remove it. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-21drivers: phy: add Innosilicon DSI-DPHY driverChris Morgan3-0/+689
Add support for the Innosilicon DSI-DPHY driver for Rockchip SOCs. The driver was ported from Linux and tested on a Rockchip RK3566 based device to query the panel ID via a DSI command. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-16phy: renesas: Add Renesas Ethernet SERDES driver for R-Car S4-8Marek Vasut5-0/+396
Add Renesas Ethernet SERDES driver for R-Car S4-8 (r8a779f0). The datasheet describes initialization procedure without any information about registers' name/bits. So, this is all black magic to initialize the hardware. Especially, all channels should be initialized at once. This driver is imported and adjusted from Linux 6.3-rc1 commit: 50133cd3e8dd1 ("phy: renesas: r8a779f0-eth-serdes: Remove retry code in .init()") Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-04-07phy: Add .set_mode and .set_speed callbacksMarek Vasut1-0/+22
Add two new callbacks matching the Linux ones. The .set_mode is used to set PHY mode and submode, where mode is either USB, Ethernet, and so on, while submode is e.g. for Ethernet case RGMII, RMII, and so on. The .set_speed is used to configure link speed into the PHY. Unlike the existing configure callback, which is used to pass arbitrary custom information to the PHY, these two callbacks are used to pass standardized set of information to the PHY. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-03-29phy: ti: j721e-wiz: Add support to enable LN23 Type-C swapSinthu Raja1-2/+22
The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the USB PHY that is integrated into the SerDes IP. The WIZ control register has to be configured to support this lane swap feature. The support for swapping lanes 2 and 3 is missing and therefore add support to configure the control register to swap between lanes 2 and 3 if PHY type is USB. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2023-03-29phy: ti: j721e-wiz: Manage TypeC lane swap if typec-dir-gpios not specifiedSinthu Raja1-9/+29
It's possible that the Type-C plug orientation on the DIR line will be implemented through hardware design. In that situation, there won't be an external GPIO line available, but the driver still needs to address this since the DT won't use the typec-dir-gpios property. Add code to handle LN10 Type-C swap if typec-dir-gpios property is not specified in DT. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2023-03-14Merge tag 'v2023.04-rc4' into nextTom Rini4-1/+513
Prepare v2023.04-rc4 Signed-off-by: Tom Rini <trini@konsulko.com>
2023-03-02phy: phy-mtk-tphy: add support mt8195Chunfeng Yun1-10/+81
The T-PHY controller is designed to use use PLL integer mode, but in fact use fractional mode for some ones on mt8195 by mistake, this causes signal degradation (e.g. eye diagram test fail), fix it by switching PLL to 26Mhz from default 48Mhz to improve signal quality. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2023-03-02phy: phy-mtk-tphy: remove macros to prepare bitfield valueChunfeng Yun1-75/+47
Prefer to make use of FIELD_PREP() macro to prepare bitfield value, then no need local macros anymore. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2023-02-28drivers: phy: add naneng combphy for rk3568Jagan Teki3-0/+449
RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers share one pipe interface for each combo phy, here is the diagram of the complex connection. +----------------+ | | +------+ | USB3 OTG CTRL0 |---->| | | | | | +------------+ +----------------+ | PIPE | | | | MUX |---->| Combo PHY0 | +----------------+ | | | | | | | | +------------+ | SATA CTRL0 |---->| | | | +------+ +----------------+ +----------------+ | | +------+ | USB3 HOST CTRL1|---->| | | | | | +------------+ +----------------+ | PIPE | | | | MUX |---->| Combo PHY1 | +----------------+ | | | | | |---->| | +------------+ | SATA CTRL1 | -->| | | | | +------+ +----------------+ | | +----------------+ | | | | +------+ | QSGMII CTRL |---->| | | | | | +------------+ +----------------+ | PIPE | | | | MUX |---->| Combo PHY2 | +----------------+ | | | | | |---->| | +------------+ | SATA CTRL2 | -->| | | | | +------+ +----------------+ | | +----------------+ | | | | | PCIe2 1-Lane |--- | | +----------------+ Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Co-developed-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28phy: rockchip-inno-usb2: Add USB2 PHY for rk3568Manoj Sai1-0/+54
RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the OTG port of PHY0 support OTG mode with charging detection function, they are similar to previous Rockchip SoCs. However, there are three different designs for RK3568 USB 2.0 PHY. 1. RK3568 uses independent USB GRF module for each USB 2.0 PHY. 2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB. 3. The two ports of USB 2.0 PHY share one interrupt. This patch only PHY1 with necessary attributes required to function USBPHY1 on U-Boot. Co-developed-by: Ren Jianing <jianing.ren@rock-chips.com> Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com> Co-developed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28phy: rockchip: inno-usb2: Add support #address_cells = 2Jagan Teki1-1/+10
New Rockchip devices have the usb phy nodes as standalone devices. These nodes have register nodes with #address_cells = 2, but only use 32 bit addresses. Adjust the driver to check if the returned address is "0", and adjust the index in that case. Derived and adjusted the similar change from linux-next with below commit <9c19c531dc98> ("phy: phy-rockchip-inno-usb2: support #address_cells = 2") Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-22phy: socionext: Add UniPhier USB3 PHY driverKunihiko Hayashi3-0/+177
Add USB3 PHY driver support to control clocks and resets needed to enable PHY. The phy_ops->init() and exit() control PHY clocks and resets only, and clocks and resets for the controller and the parent logic are enabled in advance. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-10Correct SPL uses of USB_MUSB_HOSTSimon Glass1-1/+1
This converts 2 usages of this option to the non-SPL form, since there is no SPL_USB_MUSB_HOST defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-20global: Finish CONFIG -> CFG migrationTom Rini1-4/+4
At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-19phy: rockchip: handle clock without enable functionJohn Keeping1-1/+1
If a clock doesn't supply the enable hook, clk_enable() will return -ENOSYS. In this case the clock is always enabled so there is no error and the phy initialisation should continue. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-12phy: usbphyc: use regulator_set_enable_if_allowed for disabling vbus supplyPatrick Delaunay1-1/+1
Use regulator_set_enable_if_allowed() api instead of regulator_set_enable() while disabling vbus supply. This way the driver doesn't see an error when it disable an always-on regulator for VBUS. This patch is needed for STM32MP157C-DK2 board when the regulator v3v3: buck4 used as the phy vbus supply in kernel device tree is always on with the next hack for low power use-case: &usbphyc_port0 { ... /* * Hack to keep hub active until all connected devices are suspended * otherwise the hub will be powered off as soon as the v3v3 is disabled * and it can disturb connected devices. */ connector { compatible = "usb-a-connector"; vbus-supply = <&v3v3>; }; }; Without this patch and the previous update in DT the command "usb stop" failed and the next command "usb start" cause a crash. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Marek Vasut <marex@denx.de>
2022-10-18phy: ti: j721e-wiz: add j784s4-wiz-10g module supportMatt Ranostay1-3/+72
Add support for j784s4-wiz-10g device which has two core reference clocks (e.g core_ref_clk, core_ref1_clk) which requires an additional mux selection option. Signed-off-by: Matt Ranostay <mranostay@ti.com>
2022-10-10phy: Add generic_{setup,shutdown}_phy() helpersPatrice Chotard1-0/+42
In drivers usb/host/{ehci,ohci}-generic.c, {ehci,ohci}_setup_phy() and {ehci,ohci}_shutdown_phy() shares 95% of common code. Factorize this code in new generic_{setup,shudown}_phy() functions. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
2022-09-19Merge branch 'master' into nextTom Rini1-28/+127
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-09-06phy: stm32-usbphyc: usbphyc is a clock provider of ck_usbo_48m clockPatrick Delaunay1-0/+79
ck_usbo_48m is generated by usbphyc PLL and used by OTG controller for Full-Speed use cases with dedicated Full-Speed transceiver. ck_usbo_48m is available as soon as the PLL is enabled. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-09-06phy: stm32-usbphyc: add counter of PLL consumerPatrick Delaunay1-28/+48
Add the counter of the PLL user n_pll_cons managed by the 2 functions stm32_usbphyc_pll_enable / stm32_usbphyc_pll_disable. This counter allow to remove the function stm32_usbphyc_is_init and it is a preliminary step for ck_usbo_48m introduction. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-08-26phy: Add support for drivers to enable USB on QCS404 SoCSumit Garg4-0/+422
QCS404 SoC supports two types of PHY, one supports high speed mode or USB2 PHY and the other supports super speed mode or USB3 PHY. So add corresponding PHY drivers. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-08-26phy: Move qcom SoCs specific phy drivers to qcom folderSumit Garg6-16/+17
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-07-25phy: ti: j721e-wiz: use OF data for device specific dataMatt Ranostay1-28/+60
Move device specific data into OF data structure so it is easier to maintain and we can get rid of if statements. Based on: https://lore.kernel.org/linux-phy/20220526064121.27625-1-rogerq@kernel.org/T/#u Cc: Roger Quadros <rogerq@kernel.org> Signed-off-by: Matt Ranostay <mranostay@ti.com>
2022-07-18phy: sun4i-usb: Add D1 variantSamuel Holland1-0/+10
D1 has a register layout like A100 and H616, with the moved SIDDQ bit. Unlike H616 it does not have any dependencies between PHY instances. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-07-18phy: sun4i-usb: Rework HCI PHY (aka "pmu_unk1") handlingAndre Przywara1-18/+14
As Icenowy pointed out, newer manuals (starting with H6) actually document the register block at offset 0x800 as "HCI controller and PHY interface", also describe the bits in our "PMU_UNK1" register. Let's put proper names to those "unknown" variables and symbols. While we are at it, generalise the existing code by allowing a bitmap of bits to clear and set, to cover newer SoCs: The A100 and H616 use a different bit for the SIDDQ control. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-07-18phy: sun4i-usb: Drop use of arch-specific headersSamuel Holland1-2/+0
Since commit 089ffd0aedb7 ("phy: sun4i-usb: Use CLK and RESET support") neither of these headers is used. Dropping them allows the driver to be architecture-independent. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-07-18sunxi: Move INITIAL_USB_SCAN_DELAY to driver KconfigSamuel Holland1-0/+10
This option is used only by the phy-sun4i-usb driver, which does not inherently depend on the ARM architecture. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-07-13phy: mtk-tphy: add support for MediaTek MT7621 SoCWeijie Gao1-1/+1
This patch makes mtk-tphy driver available for MediaTek MT7621 SoC Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-07-11Merge branch 'next'Tom Rini3-0/+223
2022-07-06phy: nuvoton: add NPCM7xx phy control driverJim Liu3-0/+223
add BMC NPCM750 phy control driver Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-26sunxi: usb: convert PHY GPIO functions to DMAndre Przywara1-26/+33
The Allwinner USB PHY driver is still using the legacy GPIO interface, which is now implemented by the DM_GPIO compat functions. Those seem to have some design flaws, as setting the direction, then later setting the value will not work, if the DM_GPIO driver is implementing set_flags. Fix this by using the dm_ version of the direct GPIO interface, which uses struct gpio_desc structs to handle requested GPIOs, and actually keeps the flags we set earlier. This fixes USB operation on boards which need to toggle the VBUS supply via a GPIO, like the Teres-I laptop or the BananaPi M2 Berry board. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reported-by: Milan P. Stanić <mps@arvanta.net> Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-05-18phy: zynqmp: Increase timeout value to 10msAshok Reddy Soma1-1/+1
Observing psgtr pll timeouts with some usb hubs and devices behind it. Increase timeout to 10ms to take care of it. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220510131234.2650-1-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-10phy: stm32-usbphyc: stm32-usbphyc: Add DT phy tuning supportPatrice Chotard1-0/+167
Add support of phy-tuning properties for sm32-usbphyc's phy tuning aligned with v5.15 kernel bindings. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-04-12phy: phy-imx8mq-usb: Add support for i.MX8MP USB PHYMarek Vasut2-7/+65
Add initial support for i.MX8MP USB PHY, i.MX8MP USB is similar to the i.MX8MQ, except for clock and power domain design customization. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice-gw74xx
2022-03-30phy: bcm63xx: Don't check clk_freeSean Anderson3-12/+4
This function always succeeds, so don't check its return value. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20220115222504.617013-5-seanga2@gmail.com
2022-03-14phy: cadence: Sierra: Move the link operations from serdes phy to link deviceAswath Govindraju1-39/+20
In commit 6f46c7441a9f ("phy: cadence: Sierra: Add a UCLASS_PHY device for links"), a separate udevice of type UCLASS_PHY was created for each link. Therefore, move the corresponding link operations under the link device. Also, change the uclass of sierra phy to UCLASS_MISC as it is no longer the phy device. Fixes: 6f46c7441a9f ("phy: cadence: Sierra: Add a UCLASS_PHY device for links") Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Georgi Vlaev <g-vlaev@ti.com>
2022-03-01phy: nop-phy: Fix phy reset if no reset-gpio definedTim Harvey1-5/+7
Ensure there is a valid reset-gpio defined before using it. Fixes: f9852acdce02 ("phy: nop-phy: Fix enabling reset") Cc: Adam Ford <aford173@gmail.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-02-24clk: Rename clk_get_optional_nodevSean Anderson1-4/+4
This normalizes the name of this accessor function to put "_optional" last. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20211222171114.3091780-2-seanga2@gmail.com
2022-02-23Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usbTom Rini1-2/+3
- OMAP EHCI updates
2022-02-23phy: nop-phy: Fix enabling resetAdam Ford1-2/+3
The reset function should place the phy into reset, while the init function should take the phy out of reset. Currently the reset function takes it out of reset, and the init calls the reset. Signed-off-by: Adam Ford <aford173@gmail.com>
2022-02-22phy: phy-uclass: check the parents for physAngus Ainslie1-6/+14
The port/hub leaf nodes don't contain the phy definitions in some dts files so check the parents. Signed-off-by: Angus Ainslie <angus@akkea.ca> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-02-21Merge tag 'xilinx-for-v2022.04-rc3' of ↵Tom Rini1-2/+28
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.04-rc3 microblaze: - Fix exception handler zynqmp: - Show information about secure images - DT changes (som u-boot file removal) - Fix zynqmp_pm_cfg_obj_convert.py - Fix platform boot xilinx: - Fix bootm_size calculation - Remove GPIO_EXTRA_HEADER selection power: - Add zynqmp power management driver scsi: - Add phy support to ceva driver zynq qspi: - Fix unaligned accesses and check baudrate setup - Add support for spi memory operations net: - Fix 64bit calculation in axi_emac video: - Add missing gpio dependency for seps driver
2022-02-17usb: ehci: ehci-marvell: Update compatible string to official DT bindingsPali Rohár1-1/+1
Official DT bindings use compatible string marvell,armada-3700-ehci. Update drivers and DTS files. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17phy: marvell: a3700: Update compatible string to official DT bindingsPali Rohár1-1/+2
In commit d368e1070514 ("phy: marvell: a3700: Convert to official DT bindings in COMPHY driver") was done update to official DT bindings but compatible string of official DT bindings was not updated. Fix it now. Fixes: d368e1070514 ("phy: marvell: a3700: Convert to official DT bindings in COMPHY driver") Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-15phy: zynqmp: Add support for sata and DP phy initializationMichal Simek1-2/+28
DP is untested but just c&p from Linux driver. Sata is tested on kv260-revA board which has SATA connector populated. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/d231610160e76a2ad1b4a163e0e8db0ddc4733e2.1644226590.git.michal.simek@xilinx.com
2022-02-11phy: nop-phy: Enable reset-gpios supportAdam Ford1-3/+42
Some usb-nop-xceiv devices use a gpio take them out of reset. Add a reset function to put them into that state. This is similar to how Linux handles the usb-nop-xceiv driver. Signed-off-by: Adam Ford <aford173@gmail.com>
2022-02-08phy: cadence: Sierra: Add support for skipping configurationAswath Govindraju1-16/+42
In some cases, a single SerDes instance can be shared between two different processors, each using a separate link. In these cases, the SerDes configuration is done in an earlier boot stage. Therefore, add support to skip reconfiguring, if it is was already configured beforehand. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
generated by cgit v1.1 at 2024-08-13 18:01:08 +0000