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2022-10-18phy: ti: j721e-wiz: add j784s4-wiz-10g module supportMatt Ranostay1-3/+72
Add support for j784s4-wiz-10g device which has two core reference clocks (e.g core_ref_clk, core_ref1_clk) which requires an additional mux selection option. Signed-off-by: Matt Ranostay <mranostay@ti.com>
2022-10-10phy: Add generic_{setup,shutdown}_phy() helpersPatrice Chotard1-0/+42
In drivers usb/host/{ehci,ohci}-generic.c, {ehci,ohci}_setup_phy() and {ehci,ohci}_shutdown_phy() shares 95% of common code. Factorize this code in new generic_{setup,shudown}_phy() functions. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
2022-09-19Merge branch 'master' into nextTom Rini1-28/+127
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-09-06phy: stm32-usbphyc: usbphyc is a clock provider of ck_usbo_48m clockPatrick Delaunay1-0/+79
ck_usbo_48m is generated by usbphyc PLL and used by OTG controller for Full-Speed use cases with dedicated Full-Speed transceiver. ck_usbo_48m is available as soon as the PLL is enabled. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-09-06phy: stm32-usbphyc: add counter of PLL consumerPatrick Delaunay1-28/+48
Add the counter of the PLL user n_pll_cons managed by the 2 functions stm32_usbphyc_pll_enable / stm32_usbphyc_pll_disable. This counter allow to remove the function stm32_usbphyc_is_init and it is a preliminary step for ck_usbo_48m introduction. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-08-26phy: Add support for drivers to enable USB on QCS404 SoCSumit Garg4-0/+422
QCS404 SoC supports two types of PHY, one supports high speed mode or USB2 PHY and the other supports super speed mode or USB3 PHY. So add corresponding PHY drivers. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-08-26phy: Move qcom SoCs specific phy drivers to qcom folderSumit Garg6-16/+17
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-07-25phy: ti: j721e-wiz: use OF data for device specific dataMatt Ranostay1-28/+60
Move device specific data into OF data structure so it is easier to maintain and we can get rid of if statements. Based on: https://lore.kernel.org/linux-phy/20220526064121.27625-1-rogerq@kernel.org/T/#u Cc: Roger Quadros <rogerq@kernel.org> Signed-off-by: Matt Ranostay <mranostay@ti.com>
2022-07-18phy: sun4i-usb: Add D1 variantSamuel Holland1-0/+10
D1 has a register layout like A100 and H616, with the moved SIDDQ bit. Unlike H616 it does not have any dependencies between PHY instances. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-07-18phy: sun4i-usb: Rework HCI PHY (aka "pmu_unk1") handlingAndre Przywara1-18/+14
As Icenowy pointed out, newer manuals (starting with H6) actually document the register block at offset 0x800 as "HCI controller and PHY interface", also describe the bits in our "PMU_UNK1" register. Let's put proper names to those "unknown" variables and symbols. While we are at it, generalise the existing code by allowing a bitmap of bits to clear and set, to cover newer SoCs: The A100 and H616 use a different bit for the SIDDQ control. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-07-18phy: sun4i-usb: Drop use of arch-specific headersSamuel Holland1-2/+0
Since commit 089ffd0aedb7 ("phy: sun4i-usb: Use CLK and RESET support") neither of these headers is used. Dropping them allows the driver to be architecture-independent. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-07-18sunxi: Move INITIAL_USB_SCAN_DELAY to driver KconfigSamuel Holland1-0/+10
This option is used only by the phy-sun4i-usb driver, which does not inherently depend on the ARM architecture. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-07-13phy: mtk-tphy: add support for MediaTek MT7621 SoCWeijie Gao1-1/+1
This patch makes mtk-tphy driver available for MediaTek MT7621 SoC Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-07-11Merge branch 'next'Tom Rini3-0/+223
2022-07-06phy: nuvoton: add NPCM7xx phy control driverJim Liu3-0/+223
add BMC NPCM750 phy control driver Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-26sunxi: usb: convert PHY GPIO functions to DMAndre Przywara1-26/+33
The Allwinner USB PHY driver is still using the legacy GPIO interface, which is now implemented by the DM_GPIO compat functions. Those seem to have some design flaws, as setting the direction, then later setting the value will not work, if the DM_GPIO driver is implementing set_flags. Fix this by using the dm_ version of the direct GPIO interface, which uses struct gpio_desc structs to handle requested GPIOs, and actually keeps the flags we set earlier. This fixes USB operation on boards which need to toggle the VBUS supply via a GPIO, like the Teres-I laptop or the BananaPi M2 Berry board. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reported-by: Milan P. Stanić <mps@arvanta.net> Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-05-18phy: zynqmp: Increase timeout value to 10msAshok Reddy Soma1-1/+1
Observing psgtr pll timeouts with some usb hubs and devices behind it. Increase timeout to 10ms to take care of it. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220510131234.2650-1-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-10phy: stm32-usbphyc: stm32-usbphyc: Add DT phy tuning supportPatrice Chotard1-0/+167
Add support of phy-tuning properties for sm32-usbphyc's phy tuning aligned with v5.15 kernel bindings. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-04-12phy: phy-imx8mq-usb: Add support for i.MX8MP USB PHYMarek Vasut2-7/+65
Add initial support for i.MX8MP USB PHY, i.MX8MP USB is similar to the i.MX8MQ, except for clock and power domain design customization. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice-gw74xx
2022-03-30phy: bcm63xx: Don't check clk_freeSean Anderson3-12/+4
This function always succeeds, so don't check its return value. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20220115222504.617013-5-seanga2@gmail.com
2022-03-14phy: cadence: Sierra: Move the link operations from serdes phy to link deviceAswath Govindraju1-39/+20
In commit 6f46c7441a9f ("phy: cadence: Sierra: Add a UCLASS_PHY device for links"), a separate udevice of type UCLASS_PHY was created for each link. Therefore, move the corresponding link operations under the link device. Also, change the uclass of sierra phy to UCLASS_MISC as it is no longer the phy device. Fixes: 6f46c7441a9f ("phy: cadence: Sierra: Add a UCLASS_PHY device for links") Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Georgi Vlaev <g-vlaev@ti.com>
2022-03-01phy: nop-phy: Fix phy reset if no reset-gpio definedTim Harvey1-5/+7
Ensure there is a valid reset-gpio defined before using it. Fixes: f9852acdce02 ("phy: nop-phy: Fix enabling reset") Cc: Adam Ford <aford173@gmail.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-02-24clk: Rename clk_get_optional_nodevSean Anderson1-4/+4
This normalizes the name of this accessor function to put "_optional" last. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20211222171114.3091780-2-seanga2@gmail.com
2022-02-23Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usbTom Rini1-2/+3
- OMAP EHCI updates
2022-02-23phy: nop-phy: Fix enabling resetAdam Ford1-2/+3
The reset function should place the phy into reset, while the init function should take the phy out of reset. Currently the reset function takes it out of reset, and the init calls the reset. Signed-off-by: Adam Ford <aford173@gmail.com>
2022-02-22phy: phy-uclass: check the parents for physAngus Ainslie1-6/+14
The port/hub leaf nodes don't contain the phy definitions in some dts files so check the parents. Signed-off-by: Angus Ainslie <angus@akkea.ca> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-02-21Merge tag 'xilinx-for-v2022.04-rc3' of ↵Tom Rini1-2/+28
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.04-rc3 microblaze: - Fix exception handler zynqmp: - Show information about secure images - DT changes (som u-boot file removal) - Fix zynqmp_pm_cfg_obj_convert.py - Fix platform boot xilinx: - Fix bootm_size calculation - Remove GPIO_EXTRA_HEADER selection power: - Add zynqmp power management driver scsi: - Add phy support to ceva driver zynq qspi: - Fix unaligned accesses and check baudrate setup - Add support for spi memory operations net: - Fix 64bit calculation in axi_emac video: - Add missing gpio dependency for seps driver
2022-02-17usb: ehci: ehci-marvell: Update compatible string to official DT bindingsPali Rohár1-1/+1
Official DT bindings use compatible string marvell,armada-3700-ehci. Update drivers and DTS files. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17phy: marvell: a3700: Update compatible string to official DT bindingsPali Rohár1-1/+2
In commit d368e1070514 ("phy: marvell: a3700: Convert to official DT bindings in COMPHY driver") was done update to official DT bindings but compatible string of official DT bindings was not updated. Fix it now. Fixes: d368e1070514 ("phy: marvell: a3700: Convert to official DT bindings in COMPHY driver") Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-15phy: zynqmp: Add support for sata and DP phy initializationMichal Simek1-2/+28
DP is untested but just c&p from Linux driver. Sata is tested on kv260-revA board which has SATA connector populated. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/d231610160e76a2ad1b4a163e0e8db0ddc4733e2.1644226590.git.michal.simek@xilinx.com
2022-02-11phy: nop-phy: Enable reset-gpios supportAdam Ford1-3/+42
Some usb-nop-xceiv devices use a gpio take them out of reset. Add a reset function to put them into that state. This is similar to how Linux handles the usb-nop-xceiv driver. Signed-off-by: Adam Ford <aford173@gmail.com>
2022-02-08phy: cadence: Sierra: Add support for skipping configurationAswath Govindraju1-16/+42
In some cases, a single SerDes instance can be shared between two different processors, each using a separate link. In these cases, the SerDes configuration is done in an earlier boot stage. Therefore, add support to skip reconfiguring, if it is was already configured beforehand. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configurationSwapnil Jakhade1-1/+377
Add register sequences for PCIe + QSGMII PHY multilink configuration. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add support for PHY multilink configurationsSwapnil Jakhade1-8/+145
Add support for multilink configuration of Sierra PHY. Currently, maximum two links are supported. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Update single link PCIe register configurationSwapnil Jakhade1-3/+215
Add single link PCIe register configurations for no SSC and internal SSC. Also, add missing PMA lane registers for external SSC. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operationSwapnil Jakhade1-1/+40
PIPE phy status is used to communicate the completion of several PHY functions. Check if PHY is ready for operation while configured for PIPE mode during startup. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Check cmn_ready assertion during PHY power onSwapnil Jakhade1-0/+35
Check if PMA cmn_ready is set indicating the startup process is complete. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add PHY PCS common register configurationsSwapnil Jakhade1-0/+38
Add PHY PCS common register configuration sequences for single link. Update single link PCIe register sequence accordingly. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra ↵Swapnil Jakhade1-6/+6
documentation No functional change. Rename some regmap variables as mentioned in Sierra register description documentation. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add support to get SSC type from device tree.Swapnil Jakhade1-1/+5
Add support to get SSC type from DT. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Prepare driver to add support for multilink configurationsSwapnil Jakhade1-53/+135
Sierra driver currently supports single link configurations only. Prepare driver to support multilink multiprotocol configurations along with different SSC modes. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCEAswath Govindraju1-1/+1
Fix the condition for setting P_ENABLE_FORCE bit, by syncing with the driver in kernel. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clockAswath Govindraju1-13/+210
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's possible to select one of these two inputs from device tree. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add a UCLASS_PHY device for linksAswath Govindraju1-41/+75
Add a driver of type UCLASS_PHY for each of the link nodes in the serdes instance. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callbackKishon Vijay Abraham I1-0/+2
Add missing clk_disable_unprepare() in cdns_sierra_phy_remove(). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy"Kishon Vijay Abraham I1-10/+15
Instead of having separate structure members for each input clock, add an array for the input clocks within "struct cdns_sierra_phy". This is in preparation for adding more input clocks required for supporting additional clock combination. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Move all reset_control_get*() to a separate functionKishon Vijay Abraham I1-0/+19
No functional change. Group devm_reset_control_get() and devm_reset_control_get_optional() to a separate function. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Move all clk_get_*() to a separate functionKishon Vijay Abraham I1-22/+35
No functional change. Group all devm_clk_get_optional() to a separate function. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodesKishon Vijay Abraham I1-0/+4
Cadence Sierra PHY driver registers PHY using devm_phy_create() for all sub-nodes of Sierra device tree node. However Sierra device tree node can have sub-nodes for the various clocks in addtion to the PHY. Use devm_phy_create() only for nodes with name "phy" (or "link" for old device tree) which represent the actual PHY. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Fix PHY power_on sequenceKishon Vijay Abraham I1-1/+6
Commit 39b823381d9d ("phy: cadence: Add driver for Sierra PHY") de-asserts PHY_RESET even before the configurations are loaded in phy_init(). However PHY_RESET should be de-asserted only after all the configurations has been initialized, instead of de-asserting in probe. Fix it here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
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