aboutsummaryrefslogtreecommitdiff
path: root/drivers/phy
AgeCommit message (Collapse)AuthorFilesLines
2020-07-22phy: Add Rockchip PCIe PHY driverJagan Teki3-0/+279
Add the Rockchip PCIe PHY driver as part of Generic PHY framework. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-16phy: omap-usb2-phy: disable phy charger detectBin Liu1-5/+28
AM654x PG1.0 has a silicon bug that D+ is pulled high after POR, which could cause enumeration failure with some USB hubs. Disabling the USB2_PHY Charger Detect function will put D+ into the normal state. Using property "ti,dis-chg-det-quirk" in the DT usb2-phy node to enable this workaround for AM654x PG1.0. Signed-off-by: Bin Liu <b-liu@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
2020-06-03Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini1-2/+4
- H6 emac support - USB PHY H6 logic alignment
2020-06-01phy: sun4i-usb: Align H6 initialization logic with the kernelRoman Stratiienko1-2/+4
H6 SOC needs additional initialization of PHY registers. Corresponding changes can be found in the kernel patch [1]. Without this changes there is no enumeration of 'musb' gadget. [1] - https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ae409cc7c3cdb9ac4a1dba3eae70efec3d6b6c79 Fixes: 35fa673e0e5f ("sunxi: phy: Add USB PHY support for Allwinner H6") Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-29phy: rockchip: Add Rockchip USB TypeC PHY driverJagan Teki3-0/+804
Add USB TYPEC PHY driver for rockchip platform. Referenced from Linux TypeC PHY driver, currently supporting usb3-port and dp-port need to add it in the future. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29phy: rockchip: Add Rockchip USB2PHY driverJagan Teki4-0/+333
Add Rockchip USB2PHY driver with initial support. This will help to use it for EHCI controller in host mode, and USB 3.0 controller in otg mode. More functionality like charge, vbus detection will add it in future changes. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-25phy: Fix possible NULL pointer deferenceVignesh Raghavendra1-5/+5
It is possible that users of generic_phy_*() APIs may pass a valid struct phy pointer but phy->dev can be NULL, leading to NULL pointer deference in phy_dev_ops(). So call generic_phy_valid() to verify that phy and phy->dev are both valid. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass12-0/+12
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop linux/delay.h from common headerSimon Glass15-0/+15
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop log.h from common headerSimon Glass16-0/+16
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop image.h from common headerSimon Glass1-1/+2
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-11phy: Use _nodev naming convention if non-device clientsJagan Teki1-2/+2
Clients that are requesting some of uclass API's without a device (with ofnode) usually have _nodev naming convention. - clk_get_by_index_nodev - clk_get_by_name_nodev - reset_get_by_index_nodev - gpio_request_by_name_nodev So, update the same naming convention PHY framework. This doesn't change the existing functionality. Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-02phy: phy-mtk-tphy: add a new reference clockChunfeng Yun1-3/+18
Usually the digital and analog phys use the same reference clock, but some platforms have two separate reference clocks for each of them, so add another optional clock to support them. In order to keep the clock names consistent with PHY IP's, change the da_ref for analog phy and ref clock for digital phy. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
2020-05-02phy: phy-mtk-tphy: add support new versionChunfeng Yun1-5/+63
The new version removes all shared banks between multi-phys Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
2020-05-02phy: phy-mtk-tphy: add support USB physChunfeng Yun1-9/+218
Support USB2 and USB3 PHY with shared banks when support multi-phys Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
2020-05-02phy: Add API for a bulk of physChunfeng Yun1-0/+97
This patch adds a "bulk" API to the phy API in order to get/init/exit/power on/off a group of phys associated with a device. The bulk API will avoid adding a copy of the same code to manage a group of phys in drivers. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-28phy: meson: add GXBB PHY driverBeniamino Galvani3-0/+244
This adds support for the USB PHY found on Amlogic GXBB SoCs. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-20phy: meson-gxl-usb: add set_mode call to force switch to peripheral modeNeil Armstrong2-18/+56
Add set_mode function in the Amlogic GXL PHYs that will be called by the arch code to switch PHYs from/to gadget mode. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-20generic-phy: add generic_phy_get_by_node()Neil Armstrong1-5/+11
Add generic_phy_get_by_node() to get a PHY phandle from a node instead of a udevice. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com> [narmstrong: fixed by including ofnode.h in generic-phy.h]
2020-02-05dm: core: Create a new header file for 'compat' featuresSimon Glass15-0/+17
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: core: Require users of devres to include the headerSimon Glass6-0/+6
At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-01-26Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini1-0/+12
- Libre Computer ALL-H3-IT/ALL-H5-CC board (Chen-Yu Tsai) - Allwinner R40 Ethernet, usb phy enablement (Andre Przywara) - Sunxi auto load from 128KB MMC offset (Andre Przywara) - Orange Pi Win Ethernet phy enablement (Jernej Skrabec)
2020-01-24phy: sun4i-usb: Add Allwinner R40 supportAndre Przywara1-0/+12
Since every Allwinner USB PHY seems to be slightly different from each other, we need to add the compatible string and the respective data structure to make it work on the R40/V40 SoC. Nothing spectacular this time, just one less USB controller than the H3. Copied from the Linux kernel. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-20phy: omap-usb2-phy: Add support for AM654 USB2 PHYVignesh Raghavendra1-0/+17
AM654 SoC has USB2 PHY which is similar to existing USB2 PHYs on OMAP SoCs. Add support for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20phy: omap-usb2-phy: Fix warnings when built for ARM64Vignesh Raghavendra1-3/+2
Below warning is seen when this driver is built for devices with 64 bit physical address space. drivers/phy/omap-usb2-phy.c: In function ‘omap_usb2_phy_probe’: drivers/phy/omap-usb2-phy.c:187:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] priv->phy_base = (void *)base; ^ Fix this by using dev_read_addr_ptr() instead of dev_read_addr(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-16phy: phy-mtk-tphy: make ref clock optionalChunfeng Yun1-1/+2
If make the ref clock optional, no need refer to fixed-clock when the ref clock is always on or comes from oscillator directly. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16phy: phy-mtk-tphy: remove the check of -ENOSYSChunfeng Yun1-2/+1
No need check -ENOSYS anymore after add dummy_enable() for fixed-clock. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2019-12-26phy: ti-pipe3: Fix SATA & USB PHY power up sequenceRoger Quadros1-17/+19
As per "Table 26-7. SATA PHY Subsystem Low-Level Programming Sequence" in TRM [1] we need to turn on SATA_PHY_TX before SATA_PHY_RX. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros <rogerq@ti.com>
2019-12-26phy: ti-pipe3: improve DPLL stability for SATA & USBRoger Quadros1-0/+193
For increased DPLL stability use the settings recommended in the TRM [1] for PHY_RX registers for SATA and USB. For SATA we need to use spread spectrum settings even though we don't have spread spectrum enabled. The suggested non-spread spectrum settings don't work. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros <rogerq@ti.com>
2019-12-26phy: ti-pipe3: Introduce mode property in driver dataRoger Quadros1-6/+28
Introduce a mode property in the driver data so that we don't have to keep using "of_device_is_compatible()" throughtout the driver. No functional change. Signed-off-by: Roger Quadros <rogerq@ti.com>
2019-12-26phy: ti-pipe3: Use TRM recommended settings for SATA DPLLRoger Quadros1-7/+7
The AM572x Technical Reference Manual, SPRUHZ6H, Revised November 2016 [1], shows recommended settings for the SATA DPLL in Table 26-8. DPLL CLKDCOLDO Recommended Settings. Use those settings in the driver. The TRM does not show a value for 20MHz SYS_CLK so we use something close to the 26MHz setting. [1] - http://www.ti.com/lit/ug/spruhz6h/spruhz6h.pdf Signed-off-by: Roger Quadros <rogerq@ti.com>
2019-10-31drivers: phy: Handle gracefully NULL pointersJean-Jacques Hiblot1-5/+25
For some controllers PHYs can be optional. Handling NULL pointers without crashing nor failing, makes it easy to handle optional PHYs. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-25Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mipsTom Rini2-68/+158
- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs - bmips: various small fixes - mtmips: add new drivers for clock, reset-controller and pinctrl - mtmips: add support for high speed UART - mtmips: update/enhance drivers for SPI and ethernet - mtmips: add support for MMC
2019-10-25phy: mt76x8-usb-phy: add slew rate calibration and remove non-mt7628 partWeijie Gao2-68/+158
This patch adds slew rate calibration for mt76x8-usb-phy, removes code which belongs to mt7620, and gets rid of using syscon and regmap by using clock driver and reset controller. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-24phy: keystone-usb: handle the transition of the USB power domainJean-Jacques Hiblot1-0/+22
There is no proper power domain support for the keystone platforms. However we need to turn off the USB domains before jumping to linux or it fail to boot (observed with k2e and k2l platforms). This can be done in the PHY driver as it is dedicated only to the keystone platforms and matches the required on/off sequence. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-11phy: mediatek: add MediaTek T-PHY support for PCIeRyder Lee3-0/+374
The driver provides PHY for USB2, USB3.0, PCIe and SATA, and now we just enable PCIe. As for the other functionalities will be added gradually in upcoming days. This is adapted from the Linux version. Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2019-08-26Kconfig: Varios: Fix more SPL, TPL dependenciesAdam Ford1-1/+1
Several options are presenting themselves on a various boards where the options are clearly not used. (ie, SPL/TPL options when SPL or TPL are not defined) This patch is not attempting to be a complete list of items, but more like low hanging fruit. In some instances, I wasn't sure of DM was required, so I simply made them SPL or TPL. This patch attempts to reduce some of the menuconfig noise by defining dependencies so they don't appear when not used. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-08-12phy: add support for AM654x SERDESSekhar Nori3-0/+421
Add a new SERDES driver for TI's AM654x SoC which configures the SERDES only for PCIe. Support fo USB3 can be added later. SERDES in am654x has three input clocks (left input, external reference clock and right input) and two output clocks (left output and right output) in addition to a PLL mux clock which the SERDES uses for Clock Multiplier Unit (CMU refclock). The PLL mux clock can select from one of the three input clocks. The right output can select between left input and external reference clock while the left output can select between the right input and external reference clock. The driver has support to select PLL mux and left/right output mux as specified in device tree. Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-08phy: Add support for phy-da8xx-usbAdam Ford3-0/+71
In preparation for supporting the musb driver, this patch adds support for the usb phy associated with the musb driver. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-07-16sunxi: phy: Add USB PHY support for Allwinner H6Andre Przywara1-0/+20
The USB PHY used in the Allwinner H6 SoC has some pecularities (as usual), which require a small addition to the USB PHY driver: In this case the second PHY is PHY3, not PHY1, so we need to skip number 1 and 2 in the code. Just use the respective code from Linux for that. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-09phy: meson: add Amlogic G12A USB2 and USB3+PCIE PHY driversNeil Armstrong4-0/+570
This adds support for the USB PHYs found in the Amlogic G12A SoC Family. The USB2 PHY supports Host and/or Peripheral mode, depending on it's position. The first PHY is only used as Host, but the second supports Dual modes defined by the USB Control Glue HW in front of the USB Controllers. The second driver supports USB3 Host mode or PCIE 2.0 mode, depending on the layout of the board. Selection is done by the #phy-cells, making the mode static and exclusive. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-21phy: usbphyc: increase PLL wait timeoutPatrick Delaunay1-6/+4
wait 200us to solve USB init issue on device mode (ums and stm32prog commands) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-21phy: usbphyc: move vdda1v1 and vdda1v8 in phy_initPatrick Delaunay1-29/+31
vdda1v1 and vdda1v8 are used by the PLL. Both need to be enabled before starting the PLL. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-21phy: usbphyc: Binding update of vdda supplyPatrick Delaunay1-24/+30
Move supply vdda1v1 and vdda1v8 in usbphyc node and no more in port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-21phy: usbphyc: update xlate with DT bindingPatrick Delaunay1-9/+10
Parameter added for port 1, for example: &usbh_ehci { phys = <&usbphyc_port0>; phy-names = "usb"; vbus-supply = <&vbus_sw>; status = "okay"; }; &usbotg_hs { pinctrl-names = "default"; pinctrl-0 = <&usbotg_hs_pins_a>; phys = <&usbphyc_port1 0>; phy-names = "usb2-phy"; status = "okay"; }; Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-21phy: usbphyc: remove unused variable indexPatrick Delaunay1-2/+0
Remove unused field index in struct stm32_usbphyc_phy. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12phy: Add USB PHY driver for the MT76x8 (7628/7688) SoCStefan Roese3-0/+170
This driver is derived from this Linux driver: linux/drivers/phy/ralink/phy-ralink-usb.c The driver sets up power and host mode, but also needs to configure PHY registers for the MT7628 and MT7688. I removed the reset controller handling for the USB host and device, as it does not seem to be necessary right now. The soft reset bits for both devices are enabled by default and testing has shown (with hackish reset handling added), that USB related commands work identical with or without the reset handling. Please note that the resulting USB support is tested only very minimal. I was able to detect one of my 3 currently available USB sticks. Perhaps some further work is needed to fully support the EHCI controller integrated in the MT76x8 SoC. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-04-03phy: Also allow MESON_GXM for MESON_GXL_USB_PHYNeil Armstrong1-1/+1
The MESON_GXL_USB_PHY is also used on the Amlogic Meson GXM SoCs. Fixes: 2960e27e38 ("phy: Add Amlogic Meson USB2 & USB3 Generic PHY drivers") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-01-18phy: sun4i-usb: Use CLK and RESET supportJagan Teki1-20/+57
Now clock and reset drivers are available for respective SoC's so use clk and reset ops on phy driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Marek Vasut <marex@denx.de>
2018-12-14phy: omap_usb2: Add support for am437xJean-Jacques Hiblot1-11/+34
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-09-06 10:04:26 +0000