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2020-12-18dm: core: Update uclass_find_next_free_req_seq() for new schemeSimon Glass1-1/+1
This function current deals with req_seq which is deprecated. Update it to use the new sequence numbers, putting them above existing aliases. Rename the function to make this clear. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-18pci: Update to use new sequence numbersSimon Glass2-23/+32
Now that we know the sequence number at bind time, there is no need for special-case code in dm_pci_hose_probe_bus(). Note: the PCI_CAP_ID_EA code may need a look, but there are no test failures so I have left it as is. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-18dm: Avoid accessing seq directlySimon Glass14-56/+56
At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass5-20/+20
Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Update 'auto' declarations to be on one lineSimon Glass2-4/+2
Fix up the code style for those declarations that should now fit onto one line, which is all of them that currently do not. This is needed for dtoc to detect the structs correctly, at present. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass17-39/+39
This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass2-12/+12
Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass7-21/+21
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass25-30/+30
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Rename device_bind_ofnode() to device_bind()Simon Glass2-4/+4
This is the standard function to use when binding devices. Drop the '_ofnode' suffix to make this clear. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-23dm: pci: fsl: Correct the workaround of erratum A-007815Hou Zhiqiang2-4/+18
The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23pci: layerscape: add a way of specifying additional iommu mappingsLaurentiu Tudor2-0/+340
In the current implementation, u-boot creates iommu mappings only for PCI devices enumarated at boot time thus does not take into account more dynamic scenarios such as SR-IOV or PCI hot-plug. Add an u-boot env var and a device tree property (to be used for example in more static scenarios such as hardwired PCI endpoints that get initialized later in the system setup) that would allow two things: - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number of VFs that will ever be created for it - for hot-plug case, specify the B.D.F with which the device will show up on the PCI bus More details can be found in the included documentation: arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23pci: layerscape: move pci node search in a common functionLaurentiu Tudor1-42/+34
Fix duplication of this code by placing it in a common function. Furthermore, the resulting function will be re-used in upcoming patches. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23pci: layerscape: move per-pci device fdt fixup in a functionLaurentiu Tudor1-26/+34
Move the pci device related fdt fixup in a function in order to re-use it in a following patch. While at it, improve the error handling. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-05Merge branch 'next'Tom Rini1-1/+2
Bring in the assorted changes that have been staged in the 'next' branch prior to release. Signed-off-by: Tom Rini <trini@konsulko.com>
2020-09-25Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini2-0/+32
- Bug fixes related to PCIe, pfe, xfi, gpio, reset, vid, env, and usb on layerscape products
2020-09-24pci: layerscape: Fixup PCIe EP mode DT nodes for LX2160A rev2Hou Zhiqiang1-0/+26
LX2160A rev2 uses different PCIe controller, so EP mode DT nodes also need to be fixed up. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24arm64: a37xx: pci: Disable link training when unloading driverPali Rohár1-0/+5
As required by PCI Express spec a delay for at least 100ms after de-asserting PERST# signal is needed before link training is enabled. Linux kernels prior to 5.8 version do not automatically disable link training before de-asserting PERST# signal, therefore this requirement is not fulfilled. Above requirement is needed for proper detection of some Compex PCIe WiFi cards. Otherwise Linux kernel cannot detect it. To allow using those PCIe cards with older Linux kernel versions booted by U-Boot compiled with U-Boot a37xx pci driver, disable link training in U-Boot when unloading this pci driver. Thanks to DM_FLAG_OS_PREPARE flag, U-Boot automatically unload this driver when booting Linux kernel. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2020-09-23pci: layerscape: Fix spurious writes and panicMichael Walle1-0/+6
The fdt_fixup_pcie_ls() scans all PCI devices and assumes that all PCI root devices are layerscape PCIe controllers. Unfortunately, this is not true for the LS1028A. There is one additional static PCI root complex (this contains the networking devices) which has nothing to do with the layerscape PCIe controllers. On recent U-Boot versions this results in the following panic: "Synchronous Abort" handler, esr 0x96000044 elr: 000000009602fa04 lr : 000000009602f9f4 (reloc) elr: 00000000fbd73a04 lr : 00000000fbd739f4 x0 : 0080000002000101 x1 : 0000000000000000 x2 : 00000000fbde9000 x3 : 0000000000000001 x4 : 0000000000000000 x5 : 0000000000000030 x6 : 00000000fbdbd460 x7 : 00000000fbb3d3a0 x8 : 0000000000000002 x9 : 000000000000000c x10: 00000000ffffffe8 x11: 0000000000000006 x12: 000000000001869f x13: 0000000000000a2c x14: 00000000fbb3d2cc x15: 00000000ffffffff x16: 0000000000010000 x17: 0000000000000000 x18: 00000000fbb3fda0 x19: 0000000000000800 x20: 0000000000000000 x21: 00000001f0000000 x22: 0000000000000800 x23: 0000000000000009 x24: 00000000fbdc3c1b x25: 00000000fbdc28e5 x26: 00000000fbdcc008 x27: 00000000fbdc16e2 x28: 000000000f000000 x29: 00000000fbb3d3a0 Code: 394072a1 f94006a0 34000041 5ac00a94 (b8336814) Resetting CPU ... This bug already existed in former versions, but the spurious write was never trapped, because the destination address was a valid address (by pure luck). Make sure the PCI root is actually one of the expected PCIe layerscape controllers by matching its compatible string. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Tested-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-10PCI: mediatek: Release the resource when PCIe enable port failChuanjia Liu1-6/+13
On the mt7623 platform, if one port enable fail and other port enable succeed. It will hang on when using pci enum because the resource was not released correctly. Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com> Tested-by: Frank Wunderlich <frank-w@public-files.de>
2020-09-10PCI: mediatek: Release the resource when PCIe enable port failChuanjia Liu1-6/+13
On the mt7623 platform, if one port enable fail and other port enable succeed. It will hang on when using pci enum because the resource was not released correctly. Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com> Tested-by: Frank Wunderlich <frank-w@public-files.de>
2020-09-07Merge branch 'remove-config-nr-dram-banks-v9-2020-08-26' of ↵Tom Rini1-1/+2
https://gitlab.denx.de/u-boot/custodians/u-boot-marvell into next
2020-08-31arm64: a37xx: pci: Depends on DM_GPIOPali Rohár2-8/+3
For proper initialization of aardvark pci driver it is required to de-assert reset GPIO. So depeneds on DM_GPIO option. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31arm64: a37xx: pci: Assert PERST# signal when unloading driverPali Rohár1-6/+21
This change ensures that PCIe card is put into reset state when U-Boot stops using it. DM_FLAG_OS_PREPARE ensures that U-Boot executes driver's remove callback prior booting Linux kernel. Linux kernel pci-aardvark driver needs to reset PCIe card via PERST# signal prior initializing it. If it does not issue reset then some PCIe cards (specially Compex WiFi cards) are not detected at all. Putting PCIe card into reset state prior booting Linux kernel would ensure that card would be properly reset at time when Linux kernel starts initializing pci-aardvark driver. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31arm64: a37xx: pci: Make PCIe Reset GPIO DT compatible with Linux kernel DTPali Rohár1-3/+3
Change active-high to active-low and change DT property name from reset-gpio to reset-gpios. This format of gpio reset is used by pci-aardvark driver in Linux kernel. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-27pci: kconfig: Setup proper dependency for PCIE_ROCKCHIPMichal Simek1-0/+1
There is missing dependency for PCIE_ROCKCHIP which selects PHY_ROCKCHIP_PCIE which directly depends on ARCH_ROCKCHIP. WARNING: unmet direct dependencies detected for PHY_ROCKCHIP_PCIE Depends on [n]: ARCH_ROCKCHIP [=n] Selected by [y]: - PCIE_ROCKCHIP [=y] && PCI [=y] Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2020-08-26CONFIG_NR_DRAM_BANKS: Remove unreferenced code as its always definedStefan Roese1-1/+2
Since commit 86cf1c82850f ("configs: Migrate CONFIG_NR_DRAM_BANKS") & commit 999a772d9f24 ("Kconfig: Migrate CONFIG_NR_DRAM_BANKS"), CONFIG_NR_DRAM_BANKS is always defined with a value (4 is default). It makes no sense to still carry code that is guarded with "#ifndef CONFIG_NR_DRAM_BANKS" (and similar). This patch removes all these unreferenced code paths. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Pali Rohár <pali@kernel.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-25pci: Add PCI controller driver for OcteonTX / TX2Suneel Garapati3-0/+373
Adds support for PCI ECAM/PEM controllers found on OcteonTX or OcteonTX2 SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25pci: pci-uclass: Check validity of ofnodeSuneel Garapati1-3/+7
Add check if the referenced ofnode is valid. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25pci: pci-uclass: Add support for Alternate-RoutingID capabilitySuneel Garapati2-0/+35
If ARI capability is found on device, use it to update next function number in bus scan and also helps to skip unnecessary bdf scans. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25pci: pci-uclass: Add VF BAR map support for Enhanced AllocationSuneel Garapati1-5/+62
Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25pci: pci-uclass: Add support for Single-Root I/O VirtualizationSuneel Garapati2-0/+124
SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25pci: pci-uclass: Add support for Enhanced Allocation in BridgesSuneel Garapati1-6/+18
If Enhanced Allocation capability is present in bridges, use it to read the fixed sub-ordinate bus number. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25pci: pci-uclass: Add multi entry support for memory regionsSuneel Garapati2-3/+16
Enable PCI memory regions in ranges property to be of multiple entry. This helps to add support for SoC's like OcteonTX/TX2 where every peripheral is on PCI bus. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25pci: pci-uclass: Make DT subnode parse optionalSuneel Garapati1-1/+2
Parse subnode DT properties only if parent node is valid. Otherwise, assert is triggered on ofnode_valid in ofnode_first_subnode from dev_for_each_subnode. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25pci: pci-uclass: Fix incorrect argument in map_physmemSuneel Garapati1-2/+2
Fix argument ordering for map_physmem() called in dm_pci_map_ea_bar(). Additinally minor spelling correction. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25pci: pci-uclass: Dynamically allocate the PCI regionsStefan Roese1-6/+8
Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
2020-08-25pci: pci-uclass: Remove #ifdef CONFIG_NR_DRAM_BANKS as its always setStefan Roese1-16/+1
Since the migration to Kconfig, CONFIG_NR_DRAM_BANKS is configured for all boards. Hence we can remove the conditional compilation and the code path that will never get compiled. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-19PCI: mediatek: Add PCIe support for MT7622Chuanjia Liu1-3/+459
This patch adds PCIe support for the Mediatek MT7622 SOC. Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com> Signed-off-by: Henry Yen <henry.yen@mediatek.com>
2020-08-14drivers: pcie: add Broadcom IPROC PCIe RC driverSrinath Mannam3-0/+1295
Add support for IPROC PAXC PCIe RC driver. Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-14drivers: pci: add api to get dma regionsRayagonda Kokatanur1-0/+42
Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
2020-08-03pci: Drop dm.h inclusion from header fileSimon Glass4-2/+3
The layerscape header should not include dm.h so remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-27pci: layerscape: Add specific config entry for RC and EP mode driverHou Zhiqiang2-8/+28
Add Root Complex and Endpoint mode specific config entries, such that it's feasible to enable the RC and/or EP mode driver indepently. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27pci_ep: layerscape: Add the PCIe EP mode support for lx2160a-v2Xiaowei Bao2-2/+15
Add the PCIe EP mode support for lx2160a-v2 platform. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27pci: layerscape: Modify the ls_pcie_dump_atu functionXiaowei Bao4-14/+18
Modify the ls_pcie_dump_atu function, make it can print the INBOUND windows registers. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27pci_ep: layerscape: Add the SRIOV VFs of PF supportXiaowei Bao3-13/+42
Add the INBOUND configuration for VFs of PF. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27pci_ep: layerscape: Add Support for ls2085a and ls2080a EP modeXiaowei Bao1-5/+13
Due to the ls2085a and ls2080a use different way to set the BAR size, so add the BAR size init code here. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27pci_ep: layerscape: Add the workaround for errata A-009460Xiaowei Bao1-0/+9
The VF_BARn_REG register's Prefetchable and Type bit fields are overwritten by a write to VF's BAR Mask register. workaround: Before writing to the VF_BARn_MASK_REG register, write 0b to the PCIE_MISC_CONTROL_1_OFF register. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27pcie_ep: layerscape: Add the multiple function supportXiaowei Bao3-48/+98
Add the multiple function support for Layerscape platform, some PEXs of Layerscaple platform have more than one PF. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27pci: layerscape: Split the EP and RC driverXiaowei Bao6-497/+735
Split the RC and EP driver, and reimplement the EP driver base on the EP framework. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
generated by cgit v1.1 at 2024-09-11 14:32:37 +0000