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2019-12-09net: mvpp2: use new MVMDIO driverNevo Hed1-177/+18
This commit ports mvpp2 to use the recently introduced Marvell MDIO (MVMDIO) driver. It removes direct interaction with the SMI & XSMI busses. This commit is based in part on earlier work by Ken Ma <make@marvell.com> in Marvell's own downstream repo: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c81dc39. The above refrenced work was based on an MVMDIO implementation that never made it into U-Boot. With this patch the mvpp2 driver switches to use the new MVMDIO driver that is based on a more universal mdio-uclass implementation. Signed-off-by: Nevo Hed <nhed+github@starry.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: mvpp2: mark phy as invalid in case of missing appropriate driverGrzegorz Jaszczyk1-0/+23
If the phy doesn't match with any existing u-boot drivers, the phy framework will connect it to the generic one which uid == 0xffffffff. In this case, act as if the phy wouldn't be declared in dts. Otherwise, in case of 3310 (for which the driver doesn't exist) the link is marked as always down. Removing phy entry from dts in case of 3310 is not a good option because it is required for the phy_fw_down procedure. This patch fixes the issue with the link always down on MCBIN board. nhed: added NULL deref test. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: Igal Liberman <igall@marvell.com> Signed-off-by: Nevo Hed <nhed+github@starry.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: mvpp2x: fix traffic stuck after PHY start errorStefan Chulski1-13/+14
Issue: - Network stuck if autonegotion fails. Issue root cause: - When autonegotiation fails during port open procedure, the packet processor configuration does not finish and open procedure exits with error. - However, this doesn't prevent u-boot network framework from calling send and receive procedures. - Using transmit and receive functions of misconfigured packet processor will cause traffic to get stuck. Fix: - Continue packet processor configuration even if autonegotiation fails. Only error message is triggered in this case. - Exit transmit and receive functions if there is no PHY link indication. - U-boot network framework now calls open procedure again during next transmit initiation. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: Igal Liberman <igall@marvell.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: dp83867: refactor rgmii configurationGrygorii Strashko1-39/+36
Refactor SGMII configuration to group all settings together and reduce number of MDIO transactions. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: dp83867: io impedance is not dependent on RGMII delayGrygorii Strashko1-10/+10
Based on commit 27708eb5481b ("net: phy: dp83867: IO impedance is not dependent on RGMII delay") of mainline linux kernel. The driver would only set the IO impedance value when RGMII internal delays were enabled. There is no reason for this. Move the IO impedance block out of the RGMII delay block. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: dp83867: rework delay rgmii delay handlingGrygorii Strashko1-12/+64
Based on commit c11669a2757e ("net: phy: dp83867: Rework delay rgmii delay handling") of mainline linux kernel. The current code is assuming the reset default of the delay control register was to have delay disabled. This is what the datasheet shows as the register's initial value. However, that's not actually true: the default is controlled by the PHY's pin strapping. This patch: - insures the other direction's delay is disabled If the interface mode is selected as RX or TX delay only - validates the delay values and fail if they are not in range - checks if the board is strapped to have a delay and is configured to use "rgmii" mode and warning is generated that "rgmii-id" should have been used. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: dp83867: Add ability to disable output clockGrygorii Strashko1-17/+36
Based on commit 13c83cf8af0d ("net: phy: dp83867: Add ability to disable output clock") of mainline linux kernel. Generally, the output clock pin is only used for testing and only serves as a source of RF noise after this. It could be used to daisy-chain PHYs, but this is uncommon. Since the PHY can disable the output, make doing so an option. I do this by adding another enumeration to the allowed values of ti,clk-output-sel. The code was not using the value DP83867_CLK_O_SEL_REF_CLK as one might expect: to select the REF_CLK as the output. Rather it meant "keep clock output setting as is", which, depending on PHY strapping, might not be outputting REF_CLK. Change this so DP83867_CLK_O_SEL_REF_CLK means enable REF_CLK output. Omitting the property will leave the setting as is (which was the previous behavior in this case). Out of range values were silently converted into DP83867_CLK_O_SEL_REF_CLK. Change this so they generate an error. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: dp83867: move static initialization to .probe()Grygorii Strashko1-12/+17
Move static, one-time initialization to .probe() callback. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: ti: rename ti.c to dp83867.cGrygorii Strashko2-1/+1
The driver ti.c is actually driver for TI DP83867x PHYs, so rename it accordingly. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net/phy: Fix phy_connect() for phy addr 0Priyanka Jain1-1/+1
Fix 'mask' calculation in phy_connect() for phy addr '0'. 'mask' is getting set to '0xffffffff' for phy addr '0' in phy_connect() whereas expected value is '0'. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reported-by: tetsu-aoki via github Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-06Merge tag 'u-boot-rockchip-20191206' of ↵Tom Rini1-0/+65
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - rockchip pwm driver update to support all the SoCs - RK3308 GMAC and pinctrl support - More UART interface support on PX30 and pmugrf reg fix - Fixup on misc for eth_addr/serial# - Other updates on variant SoCs
2019-12-06net: gmac_rockchip: Add support for rk3308David Wu1-0/+65
Add the glue code to allow the rk3308 variant of the Rockchip gmac to provide network functionality. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-05Fix typo in macros, "FIRMEWARE" -> "FIRMWARE"Thomas Hebb1-2/+2
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
2019-12-03net: cpsw: Add NULL pointer checkFaiz Abbas1-0/+3
Add null pointer check to take care of out of memory errors. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-12-03Convert CONFIG_SYS_CORTINA_FW_IN_MMC et al to KconfigTom Rini1-0/+22
This converts the following to Kconfig: CONFIG_SYS_CORTINA_FW_IN_MMC CONFIG_SYS_CORTINA_FW_IN_NAND CONFIG_SYS_CORTINA_FW_IN_NOR CONFIG_SYS_CORTINA_FW_IN_REMOTE CONFIG_SYS_CORTINA_FW_IN_SPIFLASH Signed-off-by: Tom Rini <trini@konsulko.com>
2019-12-02common: Move command functions out of common.hSimon Glass1-0/+1
Move these functions into the command.h header file which is a better fit. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02common: Move ARM cache operations out of common.hSimon Glass31-0/+31
These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02common: Move mii_init() function out of common.hSimon Glass7-0/+7
This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02common: Move get_ticks() function out of common.hSimon Glass1-0/+1
This function belongs in time.h so move it over and add a comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02crc32: Use the crc.h header for crc functionsSimon Glass2-0/+2
Drop inclusion of crc.h in common.h and use the correct header directly instead. With this we can drop the conflicting definition in fw_env.h and rely on the crc.h header, which is already included. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-11-17net: gmac_rockchip: add support for px30Heiko Stuebner1-0/+69
Add the glue code to allow the px30 variant of the Rockchip gmac to provide network functionality. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-12Merge tag 'u-boot-imx-20191105' of ↵Tom Rini3-16/+69
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20191105 ------------------- i.MX8MN SoC support ROM API image download support i.MX8MM enet enabling
2019-11-08drivers: net: fsl_enetc: fix RGMII configurationMichael Walle1-0/+3
Add the missing RGMII PHY modes in which case the MAC has configure its RGMII settings. The only difference between these modes is the RX and TX delay configuration. A user might choose any RGMII mode in the device tree. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08drivers: net: fsl_enetc: set phydev->nodeMichael Walle1-0/+1
The saved ofnode is used by some PHY drivers to access the device tree node of the PHY. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-05net: fec_mxc: support i.MX8M with CLK_CCFPeng Fan2-15/+68
Add more clks for fec_mxc according to Linux Kernel 5.4.0-rc1 drivers/net/ethernet/freescale/fec_main.c. Since i.MX8MQ not support CLK_CCF, so add a check to restrict the code only effect when CONFIG_IMX8M and CONFIG_CLK_CCF both defined. Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05net: Kconfig: FEC: Add dependency on i.MX8MPeng Fan1-1/+1
Make FEC driver could be used by i.MX8M when CONFIG_FEC_MXC defined in defconfig. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-11-04net: ti: cpsw: convert to use dev/ofnode apiGrygorii Strashko1-69/+50
Conver TI CPSW driver to use dev/ofnode api. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> [trini: Add <dm/ofnode.h> to provide the prototype to ofnode] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-11-03net: ti: am65x-cpsw: fix mac tx internal delay for rgmii-rxid modeGrygorii Strashko1-1/+1
Now AM65x CPSW2G driver will disable MAC TX internal delay for PHY interface mode "rgmii-rxid" which is incorrect. Hence, fix it by keeping default value (enabled) for MAC TX internal delay when "rgmii-rxid" interface mode is selected. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03net: ti: cpsw: fix mac tx internal delay for rgmii-rxid modeGrygorii Strashko1-1/+1
Now TI CPSW driver will disable MAC TX internal delay for PHY interface mode "rgmii-rxid" which is incorrect. Hence, fix it by keeping default value (enabled) for MAC TX internal delay when "rgmii-rxid" interface mode is selected. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03net: ti: cpsw: add support for standard eth "max-speed" dt propertyGrygorii Strashko1-0/+15
This patch adds support for standard Ethernet "max-speed" DT property to allow PHY link speed limitation. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03net: ti: cpsw: move parsing of dt port's parameters in separate funcGrygorii Strashko1-24/+33
Move parsing of dt port's parameters in separate func for better code readability. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03net: ti: cpsw: enable 10Mbps link speed support in rgmii modeGrygorii Strashko1-0/+3
According to TRMs the 10Mbps link speed is supported in RGMII only when CPSW2G MAC SL is configured for External Control ("in band") mode CPSW_SL_MACCTRL.EXT_EN(18) = 1. Hence update cpsw_slave_update_link() to follow documentation. [1] https://patchwork.kernel.org/patch/10285239/ Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-10-25net: mt7628-eth: add support to isolate LAN/WAN portsWeijie Gao1-0/+32
This patch add support for mt7628-eth to isolate LAN/WAN ports mainly to prevent LAN devices from getting IP address from WAN. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25net: mt7628-eth: free rx descriptor on receiving failureWeijie Gao1-0/+3
When received a packet with an invalid length recorded in rx descriptor, we should free this rx descriptor to allow us to continue to receive following packets. Without doing so, u-boot will stuck in a dead loop trying to process this invalid rx descriptor. This patch adds a call to mt7628_eth_free_pkt() after received an invalid packet length. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25net: mt7628-eth: make phy link up detection optional via DTWeijie Gao2-29/+31
The mt7628 has an embedded ethernet switch (5 phy ports + 1 cpu port). Although in IOT mode only port0 is usable, the phy0 is still connected to the switch, not the ethernet gmac directly. This patch rewrites it and makes it optional. It can be turned on by adding mediatek,poll-link-phy = <?> explicitly into the eth node. By default the driver is switch mode with all 5 phy ports working without link detection. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25net: mt7628-eth: remove hardcoded gpio settings and regmap-based phy resetWeijie Gao1-37/+8
This patch removes hardcoded gpio settings as they have been replaced by pinctrl in dts, and also replaces regmap-based phy reset with a more generic reset controller. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-09Merge tag 'xilinx-for-v2020.01' of ↵Tom Rini6-7/+208
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx/FPGA changes for v2020.01 FPGA: - Enable fpga loading on Versal - Minor fix Microblaze: - Fix LMB configurations to support initrds - Some other cleanups Zynq: - Minor config/dt changes - Add distro boot support for usb1 and mmc1 - Remove Xilinx private boot commands and use only distro boot ZynqMP: - Kconfig cleanups, defconfig updates - Update some dt files - Add firmware driver for talking to PMUFW - Extend distro boot support for jtag - Add new IDs - Add system controller configurations - Convert code to talk firmware via mailbox or SMCs Versal: - Add board_late_init() - Add run time DT memory setup - Add DFU support - Extend distro boot support for jtag and dfu - Add clock driver - Tune mini configurations Xilinx: - Improve documentation (boot scripts, dt binding) - Enable run time initrd_high calculation - Define default SYS_PROMPT - Add zynq/zynqmp virtual defconfig Drivers: - Add Xilinx mailbox driver for talking to firmware - Clean zynq_gem for Versal - Move ZYNQ_HISPD_BROKEN to Kconfig - Wire genphy_init() in phy.c - Add Xilinx gii2rgmii bridge - Cleanup zynq_sdhci - dwc3 fix - zynq_gpio fix - axi_emac fix Others: - apalis-tk1 - clean config file
2019-10-08net: xilinx_axiemac: Fill the phy node pointer in phydevSiva Durga Prasad Paladugu1-1/+6
This patch assings the phynode pointer to the phydev node as it is needed later in the corresponding phy driver to read phy properties from DT. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08net: phy: Add gmiitorgmii converter supportSiva Durga Prasad Paladugu4-0/+194
This patch adds support for gmiitorgmii converter. This converter sits between the MAC and the external phy MAC <==> GMII2RGMII <==> RGMII_PHY. The ethernet driver probes this bridge and this bridge driver probes real phy driver and invokes the real phy functionalities as requested. This bridge just needs to be configured based on real phy negotiated speed and duplex. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08net: phy: Define init routine and register generic phy driverSiva Durga Prasad Paladugu1-0/+7
This patch define init routine for generic phy driver and registers it using phy_register as this generic phy driver also needs to be relocated incase of manual reloc. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08net: zynq_gem: Remove check for VersalSiva Durga Prasad Paladugu1-4/+0
This patch removes check for Versal platform in gem driver as it now supports clock setting through clock framework. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08net: zynq_gem: Add new versal compatible stringSiva Durga Prasad Paladugu1-0/+1
This patch adds new versal compatible string to GEM driver for Versal platform. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08net: gem: Remove DECLARE_GLOBAL_DATA_PTR from gem driverMichal Simek1-2/+0
GD is not used anywhere that's why there is no reason to have this macro in the driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08net: macb: Add sam9x60-macb compatibility stringNicolas Ferre1-0/+1
Add this new compatibility string for matching sam9x60 product macb. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2019-10-07NET: DW: fix regression for ARC boardsEugeniy Paltsev1-0/+1
The commit 642b80d256e ("net: designware: drop compatible altr, socfpga-stmmac") breaks designware ethernet for all ARC boards. It removes "altr, socfpga-stmmac" compatible from "drivers/net/designware.c" without changing compatible in the boards which use it. Fix that by adding "snps,arc-dwmac-3.70a" compatible string to "drivers/net/designware.c" and using it in ARC boards device tree. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2019-09-04net: macb: Fix rx buffer cache handlingStefan Roese1-2/+4
With commit c6d07bf440bc ("net/macb: increase RX buffer size for GEM") ethernet support does not work any more with d-cache enabled on the AT91SAM. The reason is, that MACB_RX_BUFFER_SIZE was changed from 4096 to 128 but this change was not refected in the rx_buffer flush and invalidate functions, as these also use this macro. This patch now fixes this by calculating the rx buffer size correctly again in those functions. With this change, ethernet works again reliably on my AT91SAM board. Signed-off-by: Stefan Roese <sr@denx.de> Fixes: c6d07bf440bc ("net/macb: increase RX buffer size for GEM") Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Anup Patel <anup.patel@wdc.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-09-04net: designware: drop compatible altr, socfpga-stmmacRalph Siemsen1-1/+0
The same compatible = "altr,socfpga-stmmac" appears in both drivers/net/designware.c and drivers/net/dwmac_socfgpa.c, creating ambiguity in which driver will be bound. For Intel/Altera SoC devices, dwmac_socfpga.c is the correct driver. So drop the compatible string from designware.c. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-09-04Revert "net: macb: Fixed reading MII_LPA register"Bin Meng1-1/+1
This reverts commit 1b0c9914cc75d1570359181ebd493cd5746cb0ed. Commit 1b0c9914cc75 ("net: macb: Fixed reading MII_LPA register") causes 100Mbps does not work any more with SiFive FU540 GEM on the HiFive Unleashed board. Revert it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-09-04drivers: net: fsl_enet_mdio: fix missing terminator in PCI ID arrayAlex Marginean1-0/+1
It was missing in the original submission and not having it in place causes issues with probing of PCI devices. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-09-04net: dwc_et_qos: update weak function board_interface_eth_initPatrick Delaunay1-13/+3
Align the board and driver prototype for board_interface_eth_init to avoid execution issue (the interface_type parameter is defined as int or phy_interface_t). To have a generic weak function (it should be reused by other driver) I change the prototype to use directly udevice. This prototype is added in netdev.h to allow compilation check and avoid warning when compiling with W=1 on file board/st/stm32mp1/stm32mp1.c warning: no previous prototype for 'board_interface_eth_init'\ [-Wmissing-prototypes] int board_interface_eth_init(int interface_type, .... ^~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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