aboutsummaryrefslogtreecommitdiff
path: root/drivers/net/zynq_gem.c
AgeCommit message (Expand)AuthorFilesLines
2022-04-15Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-netTom Rini1-7/+2
2022-04-10treewide: Rename PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NAMarek Behún1-1/+1
2022-04-10net: introduce helpers to get PHY interface mode from a device/ofnodeMarek Behún1-7/+2
2022-04-05net: zynq_gem: Add SGMII dynamic config supportT Karthik Reddy1-0/+46
2022-04-05net: zynq_gem: Move ethernet info print statementT Karthik Reddy1-4/+4
2022-04-05net: zynq_gem: Use shared MDIO bus support for zynqmpMichal Simek1-9/+23
2022-01-17net: gem: Workaround gmii2rgmii bridge DT node issueAshok Reddy Soma1-1/+2
2022-01-17Revert "net: gem: Disable broadcast setting"Michal Simek1-2/+0
2022-01-05net: gem: Reduce timeout of mdio phy idle status checkAshok Reddy Soma1-2/+4
2022-01-05net: zynq: Add support for PHY configuration in SGMII modeMichal Simek1-0/+20
2022-01-05net: zynq: Add support for GEM resetMichal Simek1-0/+26
2022-01-05net: zynq: Add support for mdio bus address decodingMichal Simek1-0/+3
2021-10-21net: gem: Disable broadcast settingMichal Simek1-0/+2
2021-03-30net: gem: Fix setting PCS auto-negotiation stateRobert Hancock1-8/+17
2021-02-23net: gem: Fix error path in zynq_gem_probeMichal Simek1-4/+4
2021-02-23net: gem: Enable ethernet rx clock for versalT Karthik Reddy1-6/+27
2021-02-23clk: zynq: Add dummy clock enable functionMichal Simek1-2/+2
2021-02-11net: gem: unregister mdio bus if probe failsMichael Walle1-1/+3
2020-12-18dm: Avoid accessing seq directlySimon Glass1-1/+1
2020-12-13dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass1-2/+2
2020-12-13dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass1-3/+3
2020-12-13dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass1-1/+1
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass1-2/+2
2020-09-23net: gem: Add support for more PHYs on MDIO busMichal Simek1-0/+10
2020-06-24net: gem: Disable PCS autonegotiation in case of fixed-linkMichal Simek1-0/+4
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass1-0/+1
2020-05-18common: Drop log.h from common headerSimon Glass1-0/+1
2020-05-18common: Drop net.h from common headerSimon Glass1-0/+1
2020-04-06net: zynq-gem: Setup and use mdio base separatelyMichal Simek1-6/+10
2020-04-06net: zynq_gem: Add cache flush to zynq_gem_free_pktAshok Reddy Soma1-0/+12
2020-02-28net: zynq: Free allocated buffers in case of errorMichal Simek1-5/+17
2020-02-28net: zynq_gem: Use ulong instead of u32 data typeT Karthik Reddy1-1/+1
2020-02-05dm: core: Create a new header file for 'compat' featuresSimon Glass1-0/+1
2020-02-05dm: core: Require users of devres to include the headerSimon Glass1-0/+1
2020-01-14net: zynq: Add a note about RX_BUF macroMichal Simek1-0/+1
2019-12-02common: Move ARM cache operations out of common.hSimon Glass1-0/+1
2019-10-08net: zynq_gem: Remove check for VersalSiva Durga Prasad Paladugu1-4/+0
2019-10-08net: zynq_gem: Add new versal compatible stringSiva Durga Prasad Paladugu1-0/+1
2019-10-08net: gem: Remove DECLARE_GLOBAL_DATA_PTR from gem driverMichal Simek1-2/+0
2019-04-16net: gem: Remove phy autodetection codeMichal Simek1-48/+0
2019-04-16net: zynq_gem: Modify phy supported features after max-speed was setSiva Durga Prasad Paladugu1-2/+3
2019-01-24zynq-gem: Use appropriate cache flush/invalidate for RX and TXStefan Theil1-5/+6
2018-12-03net: zynq_gem: Add check for 64-bit dma support by hardwareSiva Durga Prasad Paladugu1-1/+23
2018-12-03net: zynq_gem: Added 64-bit addressing supportVipul Kumar1-9/+54
2018-10-16net: gem: Do not setup any clock for Xilinx SoC VersalMichal Simek1-0/+4
2018-09-27net: zynq_gem: Add support for fixed-link phyMichal Simek1-8/+9
2018-09-26net: zynq_gem: Fix reading of max-speed propertySiva Durga Prasad Paladugu1-1/+2
2018-07-26net: zynq_gem: convert to use livetreeSiva Durga Prasad Paladugu1-16/+14
2018-07-26drivers: net: zynq_gem: fix phy dt node settingGrygorii Strashko1-1/+1
2018-07-02net: zynq_gem: Initialize val variable in zynq_gem_miiphy_read()Michal Simek1-1/+1
generated by cgit v1.1 at 2024-07-13 10:41:57 +0000