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path: root/drivers/net/zynq_gem.c
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2020-12-13dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass1-2/+2
This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass1-3/+3
Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass1-1/+1
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass1-2/+2
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-23net: gem: Add support for more PHYs on MDIO busMichal Simek1-0/+10
Find out MDIO bus and enable MDIO access to it if this is done via different GEM controller. Only works across GEM instances. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-06-24net: gem: Disable PCS autonegotiation in case of fixed-linkMichal Simek1-0/+4
Disable PCS autonegotiation if fixed-link node is present in device tree. This way systems with multiple GEM instances with a combination of SGMII-fixed and SGMII-PHY will work. Reported-by: Goran Marinkovic <goran.marinkovic@psi.ch> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass1-0/+1
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop log.h from common headerSimon Glass1-0/+1
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop net.h from common headerSimon Glass1-0/+1
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-06net: zynq-gem: Setup and use mdio base separatelyMichal Simek1-6/+10
Not all IPs have private MDIO bus and MDIO bus should be shared between several IPs. In past one patch tried to implement it (https://lists.denx.de/pipermail/u-boot/2018-February/319285.html) in pretty raw way but it is not the cleanest solution. This patch is just taking the part of that solution to be able to handle it over releases without conflicts. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06net: zynq_gem: Add cache flush to zynq_gem_free_pktAshok Reddy Soma1-0/+12
Add cache flush to zynq_gem_free_pkt. This is necessary because some net routines would modify this buffer in place. The cache_invalidate in the zynq_gem_recv function would cause the modifications to the buffer to overwrite the DMA from the GEM, if cache coherency is not enabled in the GEM, the next time the buffer is in use. Flushing the cache when the buffer is no longer in use by the net functions ensures that the GEM DMA is going to take place into a clean buffer. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-02-28net: zynq: Free allocated buffers in case of errorMichal Simek1-5/+17
Driver probe function is called again and again in case of error. Malloc space is getting full which is is reported by: Insufficient RAM for page table: 0x15000 > 0x14000. Please increase the size in get_page_table_size() ### ERROR ### Please RESET the board ### The patch is freeing allocated buffers on error path to avoid panic. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-02-28net: zynq_gem: Use ulong instead of u32 data typeT Karthik Reddy1-1/+1
flush_dcache_range() expects unsigned long in the arguments. Here u32 variable is unable to hold the higher address value when ddr mapped to higher addresses & flushing lower address dchache range instead which is unmapped causing to crash. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-02-05dm: core: Create a new header file for 'compat' featuresSimon Glass1-0/+1
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: core: Require users of devres to include the headerSimon Glass1-0/+1
At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-01-14net: zynq: Add a note about RX_BUF macroMichal Simek1-0/+1
Record note about reducing number of BDs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-12-02common: Move ARM cache operations out of common.hSimon Glass1-0/+1
These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-10-08net: zynq_gem: Remove check for VersalSiva Durga Prasad Paladugu1-4/+0
This patch removes check for Versal platform in gem driver as it now supports clock setting through clock framework. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08net: zynq_gem: Add new versal compatible stringSiva Durga Prasad Paladugu1-0/+1
This patch adds new versal compatible string to GEM driver for Versal platform. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08net: gem: Remove DECLARE_GLOBAL_DATA_PTR from gem driverMichal Simek1-2/+0
GD is not used anywhere that's why there is no reason to have this macro in the driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16net: gem: Remove phy autodetection codeMichal Simek1-48/+0
There is no reason to detect phy when core is doing it for us. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16net: zynq_gem: Modify phy supported features after max-speed was setSiva Durga Prasad Paladugu1-2/+3
The phydev supported features were reset in phy_set_supported() so, move the setting of driver supported features after this so that it wont lost in phy_set_supported(). Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24zynq-gem: Use appropriate cache flush/invalidate for RX and TXStefan Theil1-5/+6
The cache was only flushed before *transmitting* packets, but not when receiving them, leading to an issue where new packets were handed to the receive handler with old contents in cache. This only happens when a lot of packets are received without sending packages every now and then. Also flushing the receive buffers in the transmit function makes no sense and can be removed. Signed-off-by: Stefan Theil <stefan.theil@mixed-mode.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-12-03net: zynq_gem: Add check for 64-bit dma support by hardwareSiva Durga Prasad Paladugu1-1/+23
This patch throws an error if 64-bit support is expected but DMA hardware is not capable of 64-bit support. It also prints a debug message if DMA is capable of 64-bit but not using it. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
2018-12-03net: zynq_gem: Added 64-bit addressing supportVipul Kumar1-9/+54
This patch adds 64-bit addressing support for zynq gem. This means it can perform send and receive operations on 64-bit address buffers. Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
2018-10-16net: gem: Do not setup any clock for Xilinx SoC VersalMichal Simek1-0/+4
Xilinx SoC Versal is using fixed clock where setting rate is not supported. That's why workaround the driver till real clock driver is supported. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-09-27net: zynq_gem: Add support for fixed-link phyMichal Simek1-8/+9
Based on dt-specs fixed-link doesn't require phy-handle to be used. Fix driver to only read phy related setting when phy-handle is found. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-09-26net: zynq_gem: Fix reading of max-speed propertySiva Durga Prasad Paladugu1-1/+2
max-speed property is part of phynode and it has to be read using ofnode_read_u32_default(). This fixes the issue of incorrect max-speed read from DT. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-26net: zynq_gem: convert to use livetreeSiva Durga Prasad Paladugu1-16/+14
This patch updates the zynq gem driver to support livetree. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26drivers: net: zynq_gem: fix phy dt node settingGrygorii Strashko1-1/+1
Now zynq_gem driver will overwrite UCLASS_ETH node when PHY is connected and configured which is not correct. Use struct phydev->node instead. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
2018-07-02net: zynq_gem: Initialize val variable in zynq_gem_miiphy_read()Michal Simek1-1/+1
phyread can timeout and val will contain random value. Initialize it to zero not to report random value in case of error. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13net: gem: Check return value from memalign/mallocMichal Simek1-0/+6
Functions can return NULL in case of error that's why checking return value is needed. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13net: zynq_gem: Initialize phyreg variableMichal Simek1-1/+1
In case of phyread()/phy_setup_op() timeout code is working with uninitialized phyreg variable. Initialize this variable to make sure that code it not working with random value. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13net: zynq_gem: Fix return type for phy...()Michal Simek1-4/+4
wait_for_bit_le32 returns negative value on failure. Fix phy...() to handle these failures properly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini1-2/+1
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-13net: zynq_gem: Use max-speed property from dtSiva Durga Prasad Paladugu1-0/+9
Add support to use max-speed property from dt for determining the supported speed. Use 1000Mbps as default. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-03-23net: zynq_gem: Dont run any phy detection logic for GMII caseSiva Durga Prasad Paladugu1-1/+2
This patch bypasses phy detection logic for GMII interface and just depend on phy address received from DT. This patch is required as phy detection logic is different for some phys like xilinx phy which can be connected over SGMII and GMII interface. This fixes the issue of ethernet failures when xilinx phy is connected over GMII interface. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-24wait_bit: use wait_for_bit_le32 and remove wait_for_bitÁlvaro Fernández Rojas1-6/+6
wait_for_bit callers use the 32 bit LE version Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-29net: zynq_gem: Dont enable SGMII and PCS selectionSiva Durga Prasad Paladugu1-1/+10
Dont enable SGMII and PCS selection if internal PCS/PMA is not used, by getting the info about internal/external PCS/PMA usage from dt property "is-internal-phy". Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-02net: zynq_gem: Dont flush dummy descriptorsSiva Durga Prasad Paladugu1-4/+0
Dont flush dummy descriptors as they are already allocated from a region with dcache off. Tested this on Zynq(zc702) and ZynqMP(zcu102) boards. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02net: zynq_gem: Use wait_for_bit with non breakableSiva Durga Prasad Paladugu1-2/+2
Use wait_for_bit to be non breakable as using it with breakable causes issue of un interruptible auto negotiation. This is due to the ctrlc pressed will taken for wait_for_bit() abort during phy_read() and hence not coming out of auto negotiation. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02net: zynq_gem: Do not return -ENOSYS on successOlliver Schinagl1-5/+3
The .read_rom_hwaddr net_ops hook does not check the return value, which is why it was never caught that we are currently returning 0 if the read_rom_hwaddr function return -ENOSYS and -ENOSYS otherwise. In this case we can simplify this by just returning the result of the function. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2017-06-01dm: Rename dev_addr..() functionsSimon Glass1-1/+1
These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-03-16Merge tag 'xilinx-for-v2017.05' of git://www.denx.de/git/u-boot-microblazeTom Rini1-18/+11
Xilinx changes for v2017.05 - Move to DM clk driver - Add clk support for zynq_sdhci
2017-03-07net: zynq_gem: Fix masking of supported phydev featuresNathan Rossi1-1/+1
When the zynq_gem driver initializes the phy it sets the supported features that the phy can support and advertise. However instead of masking the supported features such that it limits the available features it sets the phy to have the exact supported features of the zynq_gem. This is problematic as it will enable features that a phy does not have or cannot advertise. Specifically this appears as an issue when using a phy that is only capable of 10/100, but the zynq_gem driver will override this and try to enable and advertise 10/100/1000. Reported-by: Arno Steffens <star@gmx.li> Fixes: 80243528ef ("net: gem: Fix gem driver on 1Gbps LAN") Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Tested-by: Arno Steffens <star@gmx.li> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2017-02-17zynq: Move zynq to clock frameworkStefan Herbrechtsmeier1-9/+0
Move the zynq to clock framework and remove unused functions as well as the CONFIG_ZYNQ_PS_CLK_FREQ configuration. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-02-17net: zynq: Add clk framework support to zynq ethernet driverStefan Herbrechtsmeier1-7/+15
If available use the clock framework to set the tx clock rate of the zynq ethernet controller. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-02-17net: zynq: Don't overwrite gem_rclk_ctrl with default valueStefan Herbrechtsmeier1-11/+5
The gem[0-1]_rclk_ctrl registers control the source of the rx clock, control and data signals and configure via ps7_init function. Don't overwrite the register with the default value. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-02-08dm: core: Replace of_offset with accessorSimon Glass1-5/+6
At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-01-10net: zynq_gem: Use clock driver for ZynqMPSiva Durga Prasad Paladugu1-0/+18
Enable and use the clock driver routine defined in clock driver toset required clock appropriately. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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