aboutsummaryrefslogtreecommitdiff
path: root/drivers/net/zynq_gem.c
AgeCommit message (Expand)AuthorFilesLines
2020-12-13dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass1-2/+2
2020-12-13dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass1-3/+3
2020-12-13dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass1-1/+1
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass1-2/+2
2020-09-23net: gem: Add support for more PHYs on MDIO busMichal Simek1-0/+10
2020-06-24net: gem: Disable PCS autonegotiation in case of fixed-linkMichal Simek1-0/+4
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass1-0/+1
2020-05-18common: Drop log.h from common headerSimon Glass1-0/+1
2020-05-18common: Drop net.h from common headerSimon Glass1-0/+1
2020-04-06net: zynq-gem: Setup and use mdio base separatelyMichal Simek1-6/+10
2020-04-06net: zynq_gem: Add cache flush to zynq_gem_free_pktAshok Reddy Soma1-0/+12
2020-02-28net: zynq: Free allocated buffers in case of errorMichal Simek1-5/+17
2020-02-28net: zynq_gem: Use ulong instead of u32 data typeT Karthik Reddy1-1/+1
2020-02-05dm: core: Create a new header file for 'compat' featuresSimon Glass1-0/+1
2020-02-05dm: core: Require users of devres to include the headerSimon Glass1-0/+1
2020-01-14net: zynq: Add a note about RX_BUF macroMichal Simek1-0/+1
2019-12-02common: Move ARM cache operations out of common.hSimon Glass1-0/+1
2019-10-08net: zynq_gem: Remove check for VersalSiva Durga Prasad Paladugu1-4/+0
2019-10-08net: zynq_gem: Add new versal compatible stringSiva Durga Prasad Paladugu1-0/+1
2019-10-08net: gem: Remove DECLARE_GLOBAL_DATA_PTR from gem driverMichal Simek1-2/+0
2019-04-16net: gem: Remove phy autodetection codeMichal Simek1-48/+0
2019-04-16net: zynq_gem: Modify phy supported features after max-speed was setSiva Durga Prasad Paladugu1-2/+3
2019-01-24zynq-gem: Use appropriate cache flush/invalidate for RX and TXStefan Theil1-5/+6
2018-12-03net: zynq_gem: Add check for 64-bit dma support by hardwareSiva Durga Prasad Paladugu1-1/+23
2018-12-03net: zynq_gem: Added 64-bit addressing supportVipul Kumar1-9/+54
2018-10-16net: gem: Do not setup any clock for Xilinx SoC VersalMichal Simek1-0/+4
2018-09-27net: zynq_gem: Add support for fixed-link phyMichal Simek1-8/+9
2018-09-26net: zynq_gem: Fix reading of max-speed propertySiva Durga Prasad Paladugu1-1/+2
2018-07-26net: zynq_gem: convert to use livetreeSiva Durga Prasad Paladugu1-16/+14
2018-07-26drivers: net: zynq_gem: fix phy dt node settingGrygorii Strashko1-1/+1
2018-07-02net: zynq_gem: Initialize val variable in zynq_gem_miiphy_read()Michal Simek1-1/+1
2018-06-13net: gem: Check return value from memalign/mallocMichal Simek1-0/+6
2018-06-13net: zynq_gem: Initialize phyreg variableMichal Simek1-1/+1
2018-06-13net: zynq_gem: Fix return type for phy...()Michal Simek1-4/+4
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini1-2/+1
2018-04-13net: zynq_gem: Use max-speed property from dtSiva Durga Prasad Paladugu1-0/+9
2018-03-23net: zynq_gem: Dont run any phy detection logic for GMII caseSiva Durga Prasad Paladugu1-1/+2
2018-01-24wait_bit: use wait_for_bit_le32 and remove wait_for_bitÁlvaro Fernández Rojas1-6/+6
2017-11-29net: zynq_gem: Dont enable SGMII and PCS selectionSiva Durga Prasad Paladugu1-1/+10
2017-06-02net: zynq_gem: Dont flush dummy descriptorsSiva Durga Prasad Paladugu1-4/+0
2017-06-02net: zynq_gem: Use wait_for_bit with non breakableSiva Durga Prasad Paladugu1-2/+2
2017-06-02net: zynq_gem: Do not return -ENOSYS on successOlliver Schinagl1-5/+3
2017-06-01dm: Rename dev_addr..() functionsSimon Glass1-1/+1
2017-03-16Merge tag 'xilinx-for-v2017.05' of git://www.denx.de/git/u-boot-microblazeTom Rini1-18/+11
2017-03-07net: zynq_gem: Fix masking of supported phydev featuresNathan Rossi1-1/+1
2017-02-17zynq: Move zynq to clock frameworkStefan Herbrechtsmeier1-9/+0
2017-02-17net: zynq: Add clk framework support to zynq ethernet driverStefan Herbrechtsmeier1-7/+15
2017-02-17net: zynq: Don't overwrite gem_rclk_ctrl with default valueStefan Herbrechtsmeier1-11/+5
2017-02-08dm: core: Replace of_offset with accessorSimon Glass1-5/+6
2017-01-10net: zynq_gem: Use clock driver for ZynqMPSiva Durga Prasad Paladugu1-0/+18