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path: root/drivers/net/zynq_gem.c
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2016-05-24Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini1-5/+9
2016-05-24net: zynq_gem: Add the passing of the phy-handle nodeDan Murphy1-5/+10
2016-05-24phy: Wire return value from phy_config()Michal Simek1-2/+1
2016-05-24net: xilinx: Handle error value from phy_startup()Michal Simek1-1/+4
2016-04-04net: zynq_gem: Add SGMII support for zynqMPSiva Durga Prasad Paladugu1-2/+11
2016-04-04net: zynq_gem: Return error incase of invalid phy addressSiva Durga Prasad Paladugu1-3/+1
2016-04-04net: gem: Allow to set the MAC from an EEPROMJoe Hershberger1-0/+18
2016-04-04net: zynq_gem: Add support for SGMII interfaceSiva Durga Prasad Paladugu1-7/+19
2016-01-27net: zynq: Change MDC setup for arm64Michal Simek1-0/+4
2016-01-25net: zynq_gem: Use shared wait_for_bitMateusz Kulikowski1-33/+2
2015-12-18net: gem: Add driver dependencies to PHYLIBMichal Simek1-4/+0
2015-12-18net: gem: Separate recv and free_pkt functionsMichal Simek1-20/+32
2015-12-18net: gem: Fix return value from recvMichal Simek1-1/+1
2015-12-18net: gem: Setup default phy address to -1Michal Simek1-1/+2
2015-12-07net: gem: Enable CTRL+C in wait_for_bitMichal Simek1-0/+6
2015-12-07net: gem: Read information about interface from DTMichal Simek1-8/+12
2015-12-07net: gem: Move driver to DMMichal Simek1-69/+110
2015-12-07net: gem: Fix miiphy_read nameMichal Simek1-2/+2
2015-12-07net: gem: Remove zynq_gem_of_init()Michal Simek1-42/+0
2015-12-07net: gem: Enable MDIO bus earlierMichal Simek1-5/+9
2015-12-07net: gem: Check if priv->phydev is validMichal Simek1-0/+2
2015-12-07net: gem: Extract phy init codeMichal Simek1-17/+30
2015-12-07net: gem: Remove phydev variableMichal Simek1-13/+10
2015-12-07net: gem: Change mii function not to use eth_device structureMichal Simek1-13/+19
2015-12-07net: gem: Change mdio_wait prototype to pass regsMichal Simek1-4/+3
2015-12-07net: gem: Do not continue if phy is not foundMichal Simek1-4/+10
2015-11-19net: zynq: Fix MDC setting for zynqMichal Simek1-1/+1
2015-11-19net: zynq: Remove unused MDCCLKDIV2 macroMichal Simek1-1/+0
2015-11-19net: zynq: Fix mdc clock division setting for 100Mbit/sMichal Simek1-2/+2
2015-11-19net: zynq: Wait till packet is sentMichal Simek1-1/+32
2015-11-19net: zynq: Disable secondary queuesEdgar E. Iglesias1-0/+26
2015-11-19net: zynq: Add dummy packet to fix packet duplication issueMichal Simek1-2/+8
2015-11-19net: zynq: Do not report TX underrunMichal Simek1-2/+0
2015-11-19net: zynq: Setup BD when structures are filledMichal Simek1-3/+3
2015-11-19net: zynq: Allocate BD_SPACE in connection to RX_BUFMichal Simek1-1/+1
2015-11-19net: zynq: Fix clearing statisticMichal Simek1-4/+3
2015-11-19net: zynq: Extend register description with offsetsMichal Simek1-15/+15
2015-11-19net: zynq: Add support for different PHY interface typesMichal Simek1-1/+8
2015-11-19net: zynq: Add debug message to phyread/phywriteMichal Simek1-1/+12
2015-11-12driver: net: Fix pointer conversion warnings for xilinx_zynqmp_epPrabhakar Kushwaha1-8/+8
2015-08-18of: clean up OF_CONTROL ifdef conditionalsMasahiro Yamada1-1/+1
2015-07-28net: gem: Extend timeout valueMichal Simek1-1/+1
2015-07-28zynq: gem: Setting up WRAP bit for one TX bdMichal Simek1-1/+2
2015-07-28zynq: gem: Increase the Rx buffer descriptors to 32Siva Durga Prasad Paladugu1-1/+1
2015-07-28zynqmp: gem: Flush the rx buffers while transmittingSiva Durga Prasad Paladugu1-3/+7
2015-07-28zynqmp: gem: Set data bus width to 64bit for arm64Siva Durga Prasad Paladugu1-1/+8
2015-04-20net: gem: Use correct type for castingMichal Simek1-1/+2
2015-04-18net: cosmetic: Fix var naming net <-> eth driversJoe Hershberger1-1/+1
2015-01-21net: gem: Use phys_addr_t instead of int for addressesMichal Simek1-2/+3
2014-05-06net: zynq: Fix sparse warnings in gemMichal Simek1-0/+1
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