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2020-06-01mtd: sf: Drop plat from sf_probeJagan Teki1-2/+0
dm_spi_slave_platdata used in sf_probe for printing plat->cs value and there is no relevant usage apart from this. We have enough debug messages available in SPI and SF areas so drop this plat get and associated bug statement. Cc: Simon Glass <sjg@chromium.org> Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-01mtd: spi: Call sst_write in _write opsJagan Teki1-6/+7
Currently spi-nor code is assigning _write ops for SST and other flashes separately.  Just call the sst_write from generic write ops and return if SST flash found, this way it avoids the confusion of multiple write ops assignment during the scan and makes it more feasible for code readability. No functionality changes. Cc: Simon Glass <sjg@chromium.org> Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-01sf: Drop spl_flash_get_sw_write_protJagan Teki5-38/+0
The get_sw_write_prot API is used to get the write-protected bits of flash by reading the status register and other wards it's API for reading register bits. 1) This kind of requirement can be achieved using existing flash operations and flash locking API calls instead of making a separate flash API. 2) Technically there is no real hardware user for this API to use in the source tree. 3) Having a flash operations API for simple register read bits also make difficult to extend the flash operations. 4) Instead of touching generic code, it is possible to have this functionality inside spinor operations in the form of flash hooks or fixups for associated flash chips. Considering all these points, this patch drops the get_sw_write_prot and associated code bases. Cc: Simon Glass <sjg@chromium.org> Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-01mtd: spi: Use CONFIG_IS_ENABLED to prevent ifdefJagan Teki2-9/+18
Use CONFIG_IS_ENABLED to prevent ifdef in sf_probe.c Cc: Simon Glass <sjg@chromium.org> Cc: Vignesh R <vigneshr@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-28mtd: spinand: toshiba: Support for new Kioxia Serial NANDYoshio Furuyama1-16/+103
Add support for new Kioxia products. The new Kioxia products support program load x4 command, and have HOLD_D bit which is equivalent to QE bit. Signed-off-by: Yoshio Furuyama <ytc-mb-yfuruyama7@kioxia.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/aa69e455beedc5ce0d7141359b9364ed8aec9e65.1584949601.git.ytc-mb-yfuruyama7@kioxia.com Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-28mtd: spinand: toshiba: Rename function name to change suffix and prefix (8Gbit)Yoshio Furuyama1-27/+27
The suffix was changed from "G" to "J" to classify between 1st generation and 2nd generation serial NAND devices (which now belong to the Kioxia brand). As reference that's 1st generation device of 1Gbit product is "TC58CVG0S3HRAIG" 2nd generation device of 1Gbit product is "TC58CVG0S3HRAIJ". The 8Gbit type "TH58CxG3S0HRAIJ" is new to Kioxia's serial NAND lineup and the prefix was changed from "TC58" to "TH58". Thus the functions were renamed from tc58cxgxsx_*() to tx58cxgxsxraix_*(). Signed-off-by: Yoshio Furuyama <ytc-mb-yfuruyama7@kioxia.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/0dedd9869569a17625822dba87878254d253ba0e.1584949601.git.ytc-mb-yfuruyama7@kioxia.com Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-22mtd: rawnand: denali: deassert write protect pinMasahiro Yamada1-0/+1
[ Linux commit 9afbe7c0140f663586edb6e823b616bd7076c00a ] If the write protect signal from this IP is connected to the NAND device, this IP can handle the WP# pin via the WRITE_PROTECT register. The Denali NAND Flash Memory Controller User's Guide describes this register like follows: When the controller is in reset, the WP# pin is always asserted to the device. Once the reset is removed, the WP# is de-asserted. The software will then have to come and program this bit to assert/de-assert the same. 1 - Write protect de-assert 0 - Write protect assert The default value is 1, so the write protect is de-asserted after the reset is removed. The driver can write to the device unless someone has explicitly cleared register before booting the kernel. The boot ROM of some UniPhier SoCs (LD4, Pro4, sLD8, Pro5) is the case; the boot ROM clears the WRITE_PROTECT register when the system is booting from the NAND device, so the NAND device becomes read-only. Set it to 1 in the driver in order to allow the write access to the device. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-05-22mtd: rawnand: denali: configure SPARE_AREA_SKIP_BYTES only for denali_splMasahiro Yamada1-9/+9
This CONFIG option is only used in denali_spl.c Move it close to SPL_NAND_DENALI, and make it depend on SPL_NAND_DENALI. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass28-0/+28
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop linux/delay.h from common headerSimon Glass20-0/+20
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop linux/bug.h from common headerSimon Glass17-0/+17
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop log.h from common headerSimon Glass40-0/+40
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop init.h from common headerSimon Glass2-0/+2
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop part.h from common headerSimon Glass1-0/+1
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop net.h from common headerSimon Glass4-0/+6
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18arm: Don't include common.h in header filesSimon Glass2-0/+4
It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop flash.h from common headerSimon Glass5-0/+5
Move this uncommon header out of the common header. Fix up some style problems in flash.h while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-11Merge tag 'u-boot-imx-20200511' of ↵Tom Rini4-88/+380
https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX for 2020.07 ---------------- - i.MX NAND and nandbxb for i.MX8M - imx8MM : new beacon devkit - imx8MQ : new pico-imx8MQ - imx8QXP : extend to enable M4, fixes - add thermal support - caches in SPL (missing board) - Fixes Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/685391011
2020-05-11sf: Add Macronix MX25R6435F SPI NOR flash to flash parameters arrayYe Li1-0/+1
On i.mx7ulp EVK board, we use MX25R6435F NOR flash, add its parameters and IDs to flash parameter array. Otherwise, the flash probe will fails. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-11spi: fix dev parameter in dev_* callsDario Binacchi1-8/+11
Probably the non-use of the device parameter by the print routines did not generate compilation errors. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-05-10mtd: nand: raw: mxs_nand changes for nandbcbHan Xu1-3/+40
Add more BCH setting mode and remove the unnecessary platform constrain Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10nand: enable the Randomizer module for i.mx7 and i.mx8Alice Guo1-1/+7
To enable the Randomizer module, set GPMI_ECCCTRL[RANDOMIZER_ENABLE] to 1, then set GPMI_ECCCOUNT[RANDOMIZER_PAGE] to select randomizer page number needed to be randomized. Signed-off-by: Alice Guo <alice.guo@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10mxs_nand: don't check zero count when ECC reading with randomizerHan Xu1-2/+3
When enabled randomizer during ECC reading, the controller reported it's erased page. Checking zero count will cause data get modified to all 0xFF. Stop checking during randomizer to workaround this issue. Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10MXS_NAND: Add clock support for iMX8Ye Li1-0/+69
Since iMX8 has enabled clock uclass, we can parse the clocks from DTB and enable them in GPMI driver. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10mtd: nand: support GPMI NAND driver for i.MX8Peng Fan3-10/+19
enable the GPMI NAND driver for i.MX8, i.MX8 use similar controller as i.MX8M - register definition for i.mx8 - DMA structure must be 32bit address Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10nand: mxs_nand: make imx8mm can use hardware BCH and randomizerAlice Guo1-1/+1
imx8mm needs to BCH encode and set NAND page number needed to be randomized modify conditional compilation Use CONFIG_IMX8M, so it apply to imx8mq/mm/mn Signed-off-by: Alice Guo <alice.guo@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10mtd: mxs_nand: fix the gf_13/14 definition issueHan Xu1-0/+2
gf_13/14 mask was not set correctly in register definition. Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10mtd: nand: mxs_nand: add i.MX6QP compatible stringHan Xu1-0/+4
add the dedicate compatible string for i.MX6QP Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10mxs_nand: Update compatible string for i.MX6SXYe Li1-0/+8
The iMX6SX uses compatible string "fsl,imx6sx-gpmi-nand" for gpmi node in DTS, so update the driver for the string Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10nand: Update SPL MXS NAND mini driverYe Li1-7/+34
Update the mini driver to add support for getting ecc info from ONFI and support read image data from page unaligned NAND address. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10mxs_nand: Add support for i.MX8MYe Li2-7/+7
Update the gpmi/apbh_dma/bch drivers and relevant registers for i.MX8M. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10nand: mxs: correct bitflip for erased NAND pagePeng Fan1-1/+17
This patch is a porting of http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/ commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38 " i.MX6QP and i.MX7D BCH module integrated a new feature to detect the bitflip number for erased NAND page. So for these two platform, set the erase threshold to gf/2 and if bitflip detected, GPMI driver will correct the data to all 0xFF. Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q with the one for i.MX6QP. " In this patch, i.MX6UL is added and threshold changed to use ecc_strength. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10nand: mxs: fix the bitflips for erased page when uncorrectable errorPeng Fan1-0/+44
This patch is porting from linux: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/ ?h=imx_4.1.15_1.0.0_ga&id=3d42fcece496224fde59f9343763fb2dfc5b0768 " We may meet the bitflips in reading an erased page(contains all 0xFF), this may causes the UBIFS corrupt, please see the log from Elie: ----------------------------------------------------------------- [ 3.831323] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry [ 3.845026] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry [ 3.858710] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry [ 3.872408] UBI error: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read 16384 bytes ... [ 4.011529] UBIFS error (pid 36): ubifs_recover_leb: corrupt empty space LEB 27:237568, corruption starts at 9815 [ 4.021897] UBIFS error (pid 36): ubifs_scanned_corruption: corruption at LEB 27:247383 [ 4.030000] UBIFS error (pid 36): ubifs_scanned_corruption: first 6569 bytes from LEB 27:247383 ----------------------------------------------------------------- This patch does a check for the uncorrectable failure in the following steps: [0] set the threshold. The threshold is set based on the truth: "A single 0 bit will lead to gf_len(13 or 14) bits 0 after the BCH do the ECC." For the sake of safe, we will set the threshold with half the gf_len, and do not make it bigger the ECC strength. [1] count the bitflips of the current ECC chunk, assume it is N. [2] if the (N <= threshold) is true, we continue to read out the page with ECC disabled. and we count the bitflips again, assume it is N2. (We read out the whole page, not just a chunk, this makes the check more strictly, and make the code more simple.) [3] if the (N2 <= threshold) is true again, we can regard this is a erased page. This is because a real erased page is full of 0xFF(maybe also has several bitflips), while a page contains the 0xFF data will definitely has many bitflips in the ECC parity areas. [4] if the [3] fails, we can regard this is a page filled with the '0xFF' data. " Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10mtd: gpmi: provide the option to use legacy bch geometryYe Li2-2/+4
Provide an option in DT to use legacy bch geometry, which compatible with the 3.10 kernel bch setting. To enable the feature, adding "fsl,legacy-bch-geometry" under gpmi-nand node. NOTICE: The feature must be enabled/disabled in both u-boot and kernel. Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10mtd: gpmi: change the BCH layout setting for large oob NANDYe Li1-69/+136
The code change updated the NAND driver BCH ECC layout algorithm to support large oob size NAND chips(oob > 1024 bytes) and proposed a new way to set ECC layout. Current implementation requires each chunk size larger than oob size so the bad block marker (BBM) can be guaranteed located in data chunk. The ECC layout always using the unbalanced layout(Ecc for both meta and Data0 chunk), but for the NAND chips with oob larger than 1k, the driver cannot support because BCH doesn’t support GF 15 for 2K chunk. The change keeps the data chunk no larger than 1k and adjust the ECC strength or ECC layout to locate the BBM in data chunk. General idea for large oob NAND chips is 1.Try all ECC strength from the minimum value required by NAND spec to the maximum one that works, any ECC makes the BBM locate in data chunk can be chosen. 2.If none of them works, using separate ECC for meta, which will add one extra ecc with the same ECC strength as other data chunks. This extra ECC can guarantee BBM located in data chunk, of course, we need to check if oob can afford it. Previous code has two methods for ECC layout setting, the legacy_calc_ecc_layout and calc_ecc_layout_by_info, the difference between these two methods is, legacy_calc_ecc_layout set the chunk size larger chan oob size and then set the maximum ECC strength that oob can afford. While the calc_ecc_layout_by_info set chunk size and ECC strength according to NAND spec. It has been proved that the first method cannot provide safe ECC strength for some modern NAND chips, so in current code, 1. Driver read NAND parameters first and then chose the proper ECC layout setting method. 2. If the oob is large or NAND required data chunk larger than oob size, chose calc_ecc_for_large_oob, otherwise use calc_ecc_layout_by_info 3. legacy_calc_ecc_layout only used for some NAND chips does not contains necessary information. So this is only a backup plan, it is NOT recommended to use these NAND chips. Signed-off-by: Han Xu <b45815@freescale.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-08configs: migrate CONFIG_SYS_MTDPARTS_RUNTIME to defconfigsPatrick Delaunay1-0/+7
Move CONFIG_SYS_MTDPARTS_RUNTIME into Kconfig done by moveconfig.py. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-04-30Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spiTom Rini5-10/+212
- distro boot support for SPI flash - sifive spi flash driver
2020-04-30mtd: spi-nor-ids: Add Spansion s25fs512s flash entryKuldeep Singh1-1/+2
Spansion "s25fs512s" flash is incorrectly decoded as "s25fl512s" on various platforms as former is not present. Add the entry. Linux already has both the flashes present. A snippet below: { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256...}, { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256...}, Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-30mtd: spi-nor-ids: Enable 4B_OPCODES for is25wp256Jagan Teki1-1/+2
IS25WP256 flash chips do support 4byte address opcodes, so enable support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-30mtd: spi-nor: Enable QE bit for ISSI flashJagan Teki1-0/+1
Enable QE bit for ISSI flash chips. QE enablement logic is similar to what Macronix has, so reuse the existing code itself. Cc: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-30Merge tag 'xilinx-for-v2020.07-rc2' of ↵Tom Rini1-1/+1
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2020.07-rc2 mmc: - Fix dt property handling via generic function clk: - Fix versal watchdog clock setting nand: - Fix zynq nand command comparison xilinx: - Enable ubifs - Sync board_late_init configurations with initrd_high setup - Make custom distro boot more verbose zynq: - Kconfig alignments - Fix nand cse configuration zynqmp: - Fix zcu104 low level qspi configuration - Small DT updates Signed-off-by: Tom Rini <trini@konsulko.com>
2020-04-29mtd: nand: spi: add support for Toshiba TC58CVG2S0HRAIJRobert Marko1-0/+10
Toshiba recently launched new revisions of their serial SLC NAND series. TC58CVG2S0HRAIJ is a refresh of previous series with minor improvements. Basic parameters are same so lets add support for this new revision. Datasheet: https://business.kioxia.com/info/docget.jsp?did=58601&prodName=TC58CVG2S0HRAIJ Signed-off-by: Robert Marko <robert.marko@sartura.hr> Tested-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-29mtd: spi-nand: Import Toshiba SPI-NAND supportRobert Marko3-1/+193
Linux has good support for Toshiba SPI-NAND, so lets import it. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Tested-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-29mtd: spi-nor: Enable dual and quad read for s25fl256s0Bacem Daassi1-1/+1
The s25fl256s0 supports dual and quad read like s25fl256s1. Enable it by adding SPI_NOR_DUAL_READ and SPI_NOR_QUAD_READ flags to the flash_info entry. Tested on real silicon and confirmed to be working. Signed-off-by: Bacem Daassi <Bacem.Daassi@cypress.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-29mtd: spi-nor-ids: Enable SPI_NOR_OCTAL_READ flag for mt35xu*Kuldeep Singh1-2/+2
Commit 658df8bd9464 ("mtd: spi-nor-core: Add octal mode support") enables octal mode(1-1-8) support in spi-nor framework. mt35xu512aba and mt35xu02g supports SINGLE and OCTAL I/O. Hence, enable SPI_NOR_OCTAL_READ flag for these flashes. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-29spi: use is_power_of_2 instead of hweight32 in spi_nor_write()Rasmus Villemoes1-4/+1
hweight32 is a somewhat expensive way to check for power-of-2. Use the is_power_of_2 helper, which does the standard and cheap idiom foo&(foo-1)==0. add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-96 (-96) Function old new delta spi_nor_write 388 292 -96 Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-27nand: brcmnand: return without disabling clockÁlvaro Fernández Rojas1-1/+8
Linux Broadcom NAND driver only disabled clock if no childs are initialized. This section of the code seems to have been accidentally dropped when it was imported in U-Boot. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-04-27ARM: zynq: Fix invalid check on NAND_CMD_NONE.Patrick van Gelder1-1/+1
The end_cmd field in the variables cmd_phase_addr and data_phase_addr contains the value 0xFF when the end_cmd equals NAND_CMD_NONE. This should be 0x00. This is caused by comparing NAND_CMD_NONE (int) with end_cmd (u8). end_cmd will be promoted by the int value -1 and therefore is not equal to 0xFF. Solved by casting NAND_CMD_NONE to u8 which will avoid int promotion. Signed-off-by: Patrick van Gelder <patrick.vangelder@nl.bosch.com> Reviewed-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-24mtd: nand: pxa3xx: fix raw read when last_chunk_size == 0Baruch Siach1-1/+1
Commit 6293b0361d9 ("mtd: nand: pxa3xx: add raw read support") added the local data_len variable in handle_data_pio() to track read size, but forgot to update the condition of drain_fifo() call. That happens to work when the layout last_chunk_size != 0. But when last_chunk_size == 0, drain_fifo() is not called to read the last chunk, which leads to "Wait timeout!!!" error. Fix this. Fixes: 6293b0361d9 ("mtd: nand: pxa3xx: add raw read support") Cc: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2020-04-06nand: raw: zynq: Do not try to probe driver if nand flash is disabledMichal Simek1-0/+5
There is no reason to continue when DT status property indicates that NAND flash is disabled. But that means that NOR flash should be present that's why try it find it out. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
generated by cgit v1.1 at 2024-08-13 06:17:13 +0000