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2023-05-01Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spiWIP/01May2023Tom Rini1-1/+116
- cadence-quadspi fixes (Apurva Nandan, Dhruva Gole) - CHIP_ERASE optimization (Marek Vasut) - fixups for s25fs512s (Takahiro Kuwano)
2023-04-30Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiWIP/30Apr2023Tom Rini1-94/+79
Please pull the second part of the sunxi pull request for this cycle. Another bunch of patches that replace old-school U-Boot hacks with proper DM based code, this time for the raw NAND flash driver, and the USB PHY VBUS detection code. Plus two smaller patches that were sitting in my inbox for a while. Gitlab CI passed. In lack of some supported board with NAND flash I couldn't really test this part, but apparently this was tested by the reviewer. I briefly ran the branch on some boards with USB-OTG, and this still worked.
2023-04-28sandbox: spi: sandbox_sf_process_cmd() missing fallthroughHeinrich Schuchardt1-0/+1
Add a missing fallthrough macro to avoid a -Wimplicit-fallthrough warning. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-28mtd: nand: sunxi: Pass the device to the init functionSamuel Holland1-19/+20
This more closely matches the U-Boot driver to the Linux version. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Michael Trimarchi <micahel@amarulasolutions.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-28mtd: nand: sunxi: Convert to the driver modelSamuel Holland1-33/+48
Clocks, resets, and pinmuxes are now handled by the driver model, so the only thing the "board" code needs to do is load the driver. This matches the pattern used by other DM raw NAND drivers (there is no NAND uclass). The actual board code is now only needed in SPL. Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-28mtd: nand: sunxi: Convert from fdtdec to ofnodeSamuel Holland1-47/+26
As a first step toward converting this driver to the driver model, use the ofnode abstraction to replace direct references to the FDT blob. Using ofnode_read_u32_index removes an extra pair of loops and makes the allwinner,rb property optional, matching the devicetree binding. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-28mtd: nand: sunxi: Remove an unnecessary checkSamuel Holland1-10/+0
Each chip is required to have a unique CS number ("reg" property) in the range 0-7, so there is no need to separately count the number of chips. Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-27sandbox64: add support for NVMXIP QSPIAbdellatif El Khlifi1-0/+7
enable NVMXIP QSPI for sandbox 64-bit Adding two NVM XIP QSPI storage devices. Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-27drivers/mtd/nvmxip: introduce QSPI XIP driverAbdellatif El Khlifi3-0/+77
add nvmxip_qspi driver under UCLASS_NVMXIP The device associated with this driver is the parent of the blk#<id> device nvmxip_qspi can be reused by other platforms. If the platform has custom settings to apply before using the flash, then the platform can provide its own parent driver belonging to UCLASS_NVMXIP and reuse nvmxip-blk driver. The custom driver can be implemented like nvmxip_qspi in addition to the platform custom settings. Platforms can use multiple NVM XIP devices at the same time by defining a DT node for each one of them. For more details please refer to doc/develop/driver-model/nvmxip_qspi.rst Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
2023-04-27drivers/mtd/nvmxip: introduce NVM XIP block storage emulationAbdellatif El Khlifi7-0/+241
add block storage emulation for NVM XIP flash devices Some paltforms such as Corstone-1000 need to see NVM XIP raw flash as a block storage device with read only capability. Here NVM flash devices are devices with addressable memory (e.g: QSPI NOR flash). The implementation is generic and can be used by different platforms. Two drivers are provided as follows. nvmxip-blk : a generic block driver allowing to read from the XIP flash nvmxip Uclass driver : When a device is described in the DT and associated with UCLASS_NVMXIP, the Uclass creates a block device and binds it with the nvmxip-blk. Platforms can use multiple NVM XIP devices at the same time by defining a DT node for each one of them. Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
2023-04-26mtd: spi-nor-core: Add fixups for s25fs512sTakahiro Kuwano1-0/+85
This patch adds fixups for s25fs512s to address the following issues from reading SFDP: - Non-uniform sectors by factory default. The setting needs to be checked and assign erase hook as needed. - Page size is wrongly advertised in SFDP. - READ_1_1_2 (3Bh/3Ch), READ_1_1_4 (6Bh/6Ch), and PP_1_1_4 (32h/34h) are not supported. - Bank Address Register (BAR) is not supported. In addition, volatile version of Quad Enable is used for safety. Based on patch by Takahiro Kuwano with s25fs_s_post_bfpt_fixup() updated to use 4-byte address commands instead of extended address mode and the page_size is fixed to 256 For future use, manufacturer code should be moved out from framework code as same as in Linux. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-04-25mtd: spi-nor: missing fallthrough in set_4byte()Heinrich Schuchardt1-0/+1
Add a missing fallthrough macro to avoid a -Wimplicit-fallthrough warning. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-04-25mtd: spi-nor: Add CHIP_ERASE optimizationMarek Vasut1-1/+30
Add support for CHIP_ERASE opcode 0xc7 . This is useful in case the entire SPI NOR is supposed to be erase at once, as is it considerably faster than 4k sector erase and even slightly faster than 64k block erase. The spi_nor_erase_chip() implementation is adapted from Linux 6.1.y as of commit 7d54cb2c26dad ("Linux 6.1.14") . The chip erase is only used in case the entire MTD device is being erased, and the chip does support this functionality. Timing figures from W25Q128JW: 16 MiB erase using 4kiB sector erase opcode 0x20 ... 107.5s 16 MiB erase using 64kiB block erase opcode 0xd8 ... 39.1s 16 MiB erase using chip erase opcode 0xc7 .......... 38.7s Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-04-22Merge tag 'u-boot-stm32-20230419' of ↵Tom Rini1-0/+3
https://source.denx.de/u-boot/custodians/u-boot-stm configs: _ Add usb_pgood_delay for ST boards _ increase malloc size for pre-reloc for stm32mp15 _ Set CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2s for stm32mp15 dts: _ Add QSPI support on STM32MP13x SoC family _ Add FMC support on STM32MP13x SoC family drivers/machine: _ pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing() _ spi: stm32_qspi: Remove useless struct stm32_qspi_flash _ rawnand: stm32_fmc2: remove unsupported EDO mode _ stm32mp: fix various array bounds checks
2023-04-22mtd: rawnand: nand_base: Handle algorithm selectionLinus Walleij1-4/+25
For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the D-Link DIR-885L and DIR-890L routers, we need to explicitly select the ECC like this in the device tree: nand-ecc-algo = "bch"; nand-ecc-strength = <1>; nand-ecc-step-size = <512>; This is handled by the Linux kernel but U-Boot core does not respect this. Fix it up by parsing the algorithm and preserve the behaviour using this property to select software BCH as far as possible. Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm] Link: https://lore.kernel.org/all/20230407134008.1939717-3-linus.walleij@linaro.org/ Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-04-22Revert "mtd: rawnand: nand_base: Handle algorithm selection"Dario Binacchi1-9/+3
It will be replaced by a more recent version which contains fixes for tests run by Tom Rini. This reverts commit ff33d3c87c2a1ab576607c2f67a9cb7690a4e7ca. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-04-19mtd: rawnand: stm32_fmc2: remove unsupported EDO modeChristophe Kerello1-0/+3
Remove the EDO mode support from as the FMC2 controller does not support the feature. Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-04-16nand: raw: octeontx: Make list staticBin Meng2-2/+2
octeontx_bch_devices and octeontx_pci_nand_deferred_devices are only referenced in the files where they are defined. Make them static. Signed-off-by: Bin Meng <bmeng@tinylab.org> Acked-by: Michael Trimarchi <michael@amarulasolutions.com> Link: https://lore.kernel.org/all/20230405143837.785082-1-bmeng@tinylab.org/ Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-04-16nand: brcmnand: add iproc supportLinus Walleij3-0/+156
Add support for the iproc Broadcom NAND controller, used in Northstar SoCs for example. Based on the Linux driver. Cc: Philippe Reynes <philippe.reynes@softathome.com> Cc: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/all/20230308214231.378013-1-linus.walleij@linaro.org/ Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-04-16mtd: rawnand: nand_base: Handle algorithm selectionLinus Walleij1-3/+9
For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the D-Link DIR-885L and DIR-890L routers, we need to explicitly select the ECC like this in the device tree: nand-ecc-algo = "bch"; nand-ecc-strength = <1>; nand-ecc-step-size = <512>; This is handled by the Linux kernel but U-Boot core does not respect this. Fix it up by parsing the algorithm and preserve the behaviour using this property to select software BCH as far as possible. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/all/20230308212851.370939-1-linus.walleij@linaro.org/ Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-03-09mtd: nand: arasan: Set ofnode valueAshok Reddy Soma1-0/+4
Ofnode value is not set, so all the DT properties are not being read and due to this default values are being used. Find nand node and set chip->flash_node value. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230224050709.30014-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09mtd: nand: arasan: Remove hardcoded bbt optionAshok Reddy Soma1-1/+0
Bad block table option is hardcoded to read from flash with NAND_BBT_USE_FLASH option. This decision should be done based on DT property. Remove this hardcoding, to be able to use DT property. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230224050709.30014-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-02mtd: Drop unused kb9202_nand driverSimon Glass2-135/+0
This is not used since time out of mind. Drop the driver and Kconfig option. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Michael Trimarchi <michael@amarulasolutions.com>
2023-03-01arm: mvebu: Add support for generating NAND kwbimagePali Rohár1-1/+3
Add a new Kconfig option CONFIG_MVEBU_SPL_BOOT_DEVICE_NAND which instruct make to generate kwbimage with NAND header. This image is used for booting from NAND flash (either SPI or parallel). Support is very simple, SPL after finishes DDR training returns back to the BootROM (via CONFIG_SPL_BOOTROM_SUPPORT option) and BootROM then loads and executes U-Boot proper. To generate correct kwbimage NAND header, it is required to set following Kconfig options: CONFIG_SYS_NAND_PAGE_SIZE CONFIG_SYS_NAND_BLOCK_SIZE CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION They are used only by make / mkimage when generating final kwbimage. CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION is a new mvebu specific Kconfig option which is set into kwbimage NAND_BADBLK_LOCATION header field. Signed-off-by: Pali Rohár <pali@kernel.org>
2023-02-27mtd: nand: Show reserved block in chip.eraseMichael Trimarchi1-1/+2
The "nand chip.erase" command always printed as bad blocks even in the case of reserved blocks. Reserved blocks are used for storing bad block tables. The patch displays "bbt reserved" when printing reserved blocks in "nand chip.erase" command. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: spinand: Fix display of unknown raw IDPatrice Chotard1-2/+3
In case ID is not found in manufacturer table, the raw ID is printed using %*phN format which is not supported by lib/vsprintf.c. The information displayed doesn't reflect the raw ID return by the unknown spi-nand. Use %02x format instead, as done in spi-nor-core.c. For example, before this patch: ERROR: spi-nand: spi_nand flash@0: unknown raw ID f74ec040 after ERROR: spi-nand: spi_nand flash@0: unknown raw ID 00 c2 26 03 Fixes: 0a6d6bae0386 ("mtd: nand: Add core infrastructure to support SPI NANDs") Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Acked-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: fix OOB R/W with Hamming ECCÁlvaro Fernández Rojas1-0/+6
Hamming ECC doesn't cover the OOB data, so reading or writing OOB shall always be done without ECC enabled. This is a problem when adding JFFS2 cleanmarkers to erased blocks. If JFFS2 clenmarkers are added to the OOB with ECC enabled, OOB bytes will be changed from ff ff ff to 00 00 00, reporting incorrect ECC errors. Fixes: 27c5b17cd1b1 ("mtd: nand: add NAND driver "library" for Broadcom STB NAND controller") Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210224080210.23686-1-noltari@gmail.com [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: support v2.1-v2.2 controllersÁlvaro Fernández Rojas1-9/+76
v2.1: tested on Netgear DGND3700v1 (BCM6368) v2.2: tested on Netgear DGND3700v2 (BCM6362) Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-6-noltari@gmail.com [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: rename page sizesÁlvaro Fernández Rojas1-2/+2
Current pages sizes apply to controllers after v3.4 Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-4-noltari@gmail.com [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: fix CS0 layoutÁlvaro Fernández Rojas1-2/+3
Only v3.3-v5.0 have a different CS0 layout. Controllers before v3.3 use the same layout for every CS. Fixes: 27c5b17cd1b1 ("mtd: nand: add NAND driver "library" for Broadcom STB NAND controller") Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-3-noltari@gmail.com [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: rename v4 registersÁlvaro Fernández Rojas1-4/+4
These registers are also used on v3.3. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-2-noltari@gmail.com [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: correctly verify erased pagesÁlvaro Fernández Rojas1-8/+11
The current code checks that the whole OOB area is erased. This is a problem when JFFS2 cleanmarkers are added to the OOB, since it will fail due to the usable OOB bytes not being 0xff. Correct this by only checking that data and ECC bytes aren't 0xff. Fixes: 02b88eea9f9c ("mtd: brcmnand: Add check for erased page bitflips") Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200512082451.771212-1-noltari@gmail.com [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: nand: brcmnand: Add support for flash-dma v0Kamal Dasu1-2/+19
This change adds support for flash dma v0.0. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: Fix ecc chunk calculation for erased page bitfipsClaire Lin1-1/+4
In brcmstb_nand_verify_erased_page(), the ECC chunk pointer calculation while correcting erased page bitflips is wrong, fix it. Fixes: 02b88eea9f9c ("mtd: brcmnand: Add check for erased page bitflips") Signed-off-by: Claire Lin <claire.lin@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: Add support for v7.3 controllerKamal Dasu1-22/+84
This change adds support for brcm NAND v7.3 controller. This controller uses a newer version of flash_dma engine and change mostly implements these differences. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: Refactored code to introduce helper functionsKamal Dasu1-38/+62
Refactored NAND ECC and CMD address configuration code to use helper functions. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: nand: Mark reserved blocksAshok Reddy Soma1-1/+2
Reserved blocks are used for storing bad block tables. With "nand bad" command, these reserved blocks are shown as bad blocks. This is leading to confusion when compared with Linux bad blocks. Hence, display "bbt reserved" when printing reserved blocks with "nand bad" command. To acheive this, return 2 which represents reserved from nand_isbad_bbt() instead of 1 in case of reserved blocks and catch it in cmd/nand.c. "nand bad" command display's hexadecimal numbers, so add "0x" prefix. Example log will show up as below. ZynqMP> nand bad Device 0 bad blocks: 0x00400000 0x16800000 0x16c00000 0x17000000 0x3d800000 0x3e400000 0xe8400000 0xff000000 (bbt reserved) 0xff400000 (bbt reserved) 0xff800000 (bbt reserved) 0xffc00000 (bbt reserved) 0x116800000 0x116c00000 0x1ff000000 (bbt reserved) 0x1ff400000 (bbt reserved) 0x1ff800000 (bbt reserved) 0x1ffc00000 (bbt reserved) Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-By: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-07mtd: Drop unused nand_plat driverSimon Glass2-66/+0
This is not used since this commit: 936478e797a SPARC: Remove Drop the driver and Kconfig option. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-07mtd: Drop unused fsmc_nand driverSimon Glass2-471/+0
This is not used since this commit: 570c3dcfc15 arm: Remove spear600 boards and the rest of SPEAr support Drop the driver and Kconfig option. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2023-02-07mtd: Drop unused fsl_upm driverSimon Glass2-188/+0
This is not used since this commit: 8d1e3cb1400 powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS support Drop the driver and Kconfig option. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com>
2023-02-07nand: Drop CONFIG_NAND_SPEARSimon Glass1-1/+0
This is not used anymore. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2023-01-27Merge tag 'xilinx-for-v2023.04-rc1' of ↵WIP/27Jan2023Tom Rini1-0/+68
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx chnages for v2023.04-rc1 makefile: - Add multi_dtb_fit dependency clk: - Handle error cases microblaze: - Disable falcon mode and cleanup code around xilinx: - Enable regular expression matching in board_fit_config_name_match() - Fix FRU handling for 0xC1 format - Fix Xilinx legacy format eeprom parsing zynqmp: - Some DT updates/cleanups - Fix IDcode for xck24 - Remove empty mini config files - Add support for k24 versal: - Remove empty mini config files versal_net: - Setup timer when runs in EL3 - Build u-boot.elf for mini configurations zynq-gem: - Add support for new compatible strings - Remove support for Avnet Ultrazedev SOM - Handle SGMII with PCS phy spi: - Add support for gigadevice parts misc: - Remove CONFIG_TARGET_VENUS ifdef - Add missing headers to remove sparse warnings
2023-01-26mtd: spi-nor: Add support for Infineon s25fs256tTakahiro Kuwano2-9/+40
Infineon S25FS256T is 256Mbit Quad SPI NOR flash. The key features and differences comparing to other Spansion/Cypress flash familes are: - 4-byte address mode by factory default - Quad mode is enabled by factory default - Supports mixture of 128KB and 64KB sectors by OTP configuration (this patch supports uniform 128KB only) Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-01-26mtd: spi-nor: Rename s25hx_t prefixTakahiro Kuwano1-21/+21
Rename s25hx_t prefix to s25 so that the single set of fixup hooks can support all other S25 families. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Acked-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-01-26mtd: spi-nor-core: Make CFRx reg fields genericTakahiro Kuwano1-4/+4
Cypress defines two flavors of configuration registers, volatile and non volatile, and both use the same bit fields. Rename the bitfields in the configuration registers so that they can be used for both flavors. Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-01-23bootstd: Add a new pre-scan priority for bootdevsSimon Glass1-2/+2
We need extensions to be set up before we start trying to boot any of the bootdevs. Add a new priority before all the others for tht sort of thing. Also add a 'none' option, so that the first one is not 0. While we are here, comment enum bootdev_prio_t fully and expand the test for the 'bootdev hunt' command. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23bootstd: Add a SPI flash bootdevSimon Glass4-0/+102
Add a bootdev for SPI flash so that these devices can be used with standard boot. It only supports loading a script. Add a special case for the label, since we want to use "spi", not "spi_flash". Enable the new bootdev on sandbox. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-20global: Finish CONFIG -> CFG migrationTom Rini2-8/+8
At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-20nxp: Finish migration of SYS_FSL_IFC_BANK_COUNT to KconfigTom Rini1-4/+0
As this is used on both ARM and PowerPC platforms, this needs to be asked in arch/Kconfig.nxp. Set the PowerPC defaults based on arch/powerpc/include/asm/config_mpc85xx.h and remove the default set in drivers/mtd/nand/raw/fsl_ifc_nand.c Signed-off-by: Tom Rini <trini@konsulko.com>
2023-01-20global: Remove unused CONFIG definesTom Rini1-6/+0
Remove some CONFIG symbols and related comments, etc, that are unused within the code itself at this point. Signed-off-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-07-14 06:55:52 +0000