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2024-04-14mtd: spinand: Add support for XTX SPINANDBruce Suen3-1/+268
Add support for XTX XT26G0xA and XT26xxxD. The driver is ported from linux-6.7.1. This driver is tested on Banana BPI-R3 with XT26G01A and XT26G12D. Link: https://lore.kernel.org/all/20240312014314.15454-1-bruce_suen@163.com Signed-off-by: Bruce Suen <bruce_suen@163.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-12-14mtd: spinand: add support for ESMT F50x1G41LBIgor Prusov3-1/+140
Adaptation of Linux commit d74c36480a67 This patch adds support for ESMT F50L1G41LB and F50D1G41LB. It seems that ESMT likes to use random JEDEC ID from other vendors. Their 1G chips uses 0xc8 from GigaDevice and 2G/4G chips uses 0x2c from Micron. For this reason, the ESMT entry is named esmt_c8 with explicit JEDEC ID in variable name. Datasheets: https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50L1G41LB(2M).pdf https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50D1G41LB(2M).pdf Signed-off-by: Igor Prusov <ivprusov@salutedevices.com> Signed-off-by: Chuanhong Guo <gch981213@gmail.com> Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Tested-by: Martin Kurbanov <mmkurbanov@sberdevices.ru> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-10-13mtd: spinand: winbond: add Winbond W25N02KV flash supportMikhail Kshevetskiy1-0/+76
Add support of Winbond W25N02KV flash Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20221010105110.446674-2-mikhail.kshevetskiy@iopsys.eu Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> (U-Boot port) Link: https://lore.kernel.org/all/20230110115843.391630-5-frieder@fris.de Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-10-13mtd: spinand: winbond: fix flash identificationMikhail Kshevetskiy1-2/+2
Winbond uses 3 bytes to identify flash: vendor_id, dev_id_0, dev_id_1, but current driver uses only first 2 bytes of it for devices identification. As result Winbond W25N02KV flash (id_bytes: EF, AA, 22) is identified as W25N01GV (id_bytes: EF, AA, 21). Fix this by adding missed identification bytes. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20221010105110.446674-1-mikhail.kshevetskiy@iopsys.eu Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> (U-Boot port) Link: https://lore.kernel.org/all/20230110115843.391630-4-frieder@fris.de Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-10-13mtd/spinand: sync supported devices with linux-5.15.43Mikhail Kshevetskiy8-101/+591
This adds more supported spinand devices from the Linux kernel implementation. This does not include the latest kernel implementation as this would require a substantial amount of extra work due to the missing ECC engine abstraction layer in U-Boot. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> (commit message) Link: https://lore.kernel.org/all/20230110115843.391630-3-frieder@fris.de Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-10-13mtd/spinand: sync core spinand code with linux-5.10.118Mikhail Kshevetskiy1-10/+14
This brings us closer to the current Linux kernel implementation of the spinand core and makes backporting features and fixes easier. This does not include the latest kernel implementation as this would require a substantial amount of extra work due to the missing ECC engine abstraction layer in U-Boot. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> (add commit message) Link: https://lore.kernel.org/all/20230110115843.391630-2-frieder@fris.de Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-10-13mtd/spinand: rework detect procedure for different READ_ID operationMikhail Kshevetskiy6-186/+143
Currently there are 3 different variants of read_id implementation: 1. opcode only. Found in GD5FxGQ4xF. 2. opcode + 1 addr byte. Found in GD5GxGQ4xA/E 3. opcode + 1 dummy byte. Found in other currently supported chips. Original implementation was for variant 1 and let detect function of chips with variant 2 and 3 to ignore the first byte. This isn't robust: 1. For chips of variant 2, if SPI master doesn't keep MOSI low during read, chip will get a random id offset, and the entire id buffer will shift by that offset, causing detect failure. 2. For chips of variant 1, if it happens to get a devid that equals to manufacture id of variant 2 or 3 chips, it'll get incorrectly detected. This patch reworks detect procedure to address problems above. New logic do detection for all variants separatedly, in 1-2-3 order. Since all current detect methods do exactly the same id matching procedure, unify them into core.c and remove detect method from manufacture_ops. This is a rework of Chuanhong Guo <gch981213@gmail.com> patch submitted to linux kernel Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Link: https://lore.kernel.org/all/20230110115843.391630-1-frieder@fris.de Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-09-24common: Drop linux/printk.h from common headerSimon Glass1-0/+1
This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-27mtd: spinand: Fix display of unknown raw IDPatrice Chotard1-2/+3
In case ID is not found in manufacturer table, the raw ID is printed using %*phN format which is not supported by lib/vsprintf.c. The information displayed doesn't reflect the raw ID return by the unknown spi-nand. Use %02x format instead, as done in spi-nor-core.c. For example, before this patch: ERROR: spi-nand: spi_nand flash@0: unknown raw ID f74ec040 after ERROR: spi-nand: spi_nand flash@0: unknown raw ID 00 c2 26 03 Fixes: 0a6d6bae0386 ("mtd: nand: Add core infrastructure to support SPI NANDs") Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Acked-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-09-18cyclic: Use schedule() instead of WATCHDOG_RESET()Stefan Roese1-2/+2
Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
2021-10-08mtd: spinand: macronix: Fix ECC Status ReadHaolin Li1-1/+9
According to datasheet, the upper four bits are reserved or used for reflecting the ECC status of the accumulated pages. The error bits number for the worst segment of the current page is encoded on lower four bits. Fix it by masking the upper bits. This same issue has been already fixed in the linux kernel by: "mtd: spinand: macronix: Fix ECC Status Read" (sha1: f4cb4d7b46f6409382fd981eec9556e1f3c1dc5d) Apply the same fix in the U-Boot driver. Signed-off-by: Haolin Li <li.haolin@qq.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-24mtd: spinand: macronix: Add support for serial NAND flashJaime Liao1-0/+46
Macronix NAND Flash devices are available in different configurations and densities. MX"35" means SPI NAND MX35"UF" , UF meands 1.8V MX35LF"2G" , 2G means 2Gbits MX35LF2G"E4" , E4 means internal ECC and Quad I/O(x4) MX35UF4GE4AD/MX35UF2GE4AD/MX35UF1GE4AD are 1.8V 4G/2Gbit serial NAND flash device with 8-bit on-die ECC https://www.mxic.com.tw/Lists/Datasheet/Attachments/7983/MX35UF4GE4AD,%201.8V,%204Gb,%20v0.00.pdf MX35UF2GE4AC/MX35UF1GE4AC are 1.8V 2G/1Gbit serial NAND flash device with 8-bit on-die ECC https://www.mxic.com.tw/Lists/Datasheet/Attachments/7974/MX35UF2GE4AC,%201.8V,%202Gb,%20v1.0.pdf Validated via normal(default) and QUAD mode by read, erase, read back, on Xilinx Zynq PicoZed FPGA board which included Macronix SPI Host(drivers/spi/spi-mxic.c). Signed-off-by: Jaime Liao <jaimeliao@mxic.com.tw> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-03-11mtd: spinand: Add WATCHDOG_RESET() in spinand_mtd_read/write()Patrice Chotard1-0/+3
In case of big area read/write on spi nand, watchdog timeout may occurs. To fix that, add WATCHDOG_RESET() in spinand_mtd_read() and spinand_mtd_write() to ensure that watchdog is reset. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-02-26mtd: nand: spi: Support GigaDevice GD5F1GQ5UExxGReto Schneider1-10/+69
The relevant changes to the already existing GD5F1GQ4UExxG support has been determined by consulting the GigaDevice product change notice AN-0392-10, version 1.0 from November 30, 2020. As the overlaps are huge, variable names have been generalized accordingly. Apart form the lowered ECC strength (4 instead of 8 bits per 512 bytes), the new device ID, and the extra quad IO dummy byte, no changes had to be taken into account. New hardware features are not supported, namely: - Power on reset - Unique ID - Double transfer rate (DTR) - Parameter page - Random data quad IO The inverted semantic of the "driver strength" register bits, defaulting to 100% instead of 50% for the Q5 devices, got ignored as the driver has never touched them anyway. The no longer supported "read from cache during block erase" functionality is not reflected as the current SPI NAND core does not support it anyway. Implementation has been tested on MediaTek MT7688 based GARDENA smart Gateways using both, GigaDevice GD5F1GQ5UEYIG and GD5F1GQ4UBYIG. Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2021-02-26mtd: nand: spi: Only one dummy byte in QUADIOHauke Mehrtens1-1/+1
The datasheet only lists one dummy byte in the 0xEB operation for the following chips: * GD5F1GQ4xExxG * GD5F1GQ4xFxxG * GD5F1GQ4UAYIG * GD5F4GQ4UAYIG Reto Schneider: - Linux patch ported to U-Boot - Checked for compatibility with GD5F1GQ4xBxxG - Fixed operation code in original commit message (0xEH -> 0xEB) Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2021-01-05Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextWIP/05Jan2021-nextTom Rini1-1/+1
Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
2021-01-05Merge tag 'v2021.01-rc5' into nextTom Rini1-16/+8
Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-05dm: core: Access device ofnode through functionsSimon Glass1-1/+1
At present ofnode is present in the device even if it is never used. With of-platdata this field is not used, so can be removed. In preparation for this, change the access to go through inline functions. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05spi: Tidy up get/set of device nodeSimon Glass1-1/+1
This code is a bit odd in that it only reads and updates the livetree version of the device ofnode. This means it won't work with flattree. Update the code to work as it was presumably intended. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-18mtd: spinand: Do not erase the block before writing a bad block markerFrieder Schrempf1-9/+0
Currently when marking a block, we use spinand_erase_op() to erase the block before writing the marker to the OOB area. Doing so without waiting for the operation to finish can lead to the marking failing silently and no bad block marker being written to the flash. In fact we don't need to do an erase at all before writing the BBM. The ECC is disabled for raw accesses to the OOB data and we don't need to work around any issues with chips reporting ECC errors as it is known to be the case for raw NAND. Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Cc: stable@vger.kernel.org Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-4-frieder.schrempf@kontron.de
2020-12-18mtd: spinand: Explicitly use MTD_OPS_RAW to write the bad block marker to OOBFrieder Schrempf1-0/+1
When writing the bad block marker to the OOB area the access mode should be set to MTD_OPS_RAW as it is done for reading the marker. Currently this only works because req.mode is initialized to MTD_OPS_PLACE_OOB (0) and spinand_write_to_cache_op() checks for req.mode != MTD_OPS_AUTO_OOB. Fix this by explicitly setting req.mode to MTD_OPS_RAW. Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-3-frieder.schrempf@kontron.de
2020-12-18mtd: spinand: Stop using spinand->oobbuf for buffering bad block markersFrieder Schrempf1-7/+7
For reading and writing the bad block markers, spinand->oobbuf is currently used as a buffer for the marker bytes. During the underlying read and write operations to actually get/set the content of the OOB area, the content of spinand->oobbuf is reused and changed by accessing it through spinand->oobbuf and/or spinand->databuf. This is a flaw in the original design of the SPI NAND core and at the latest from 13c15e07eedf ("mtd: spinand: Handle the case where PROGRAM LOAD does not reset the cache") on, it results in not having the bad block marker written at all, as the spinand->oobbuf is cleared to 0xff after setting the marker bytes to zero. To fix it, we now just store the two bytes for the marker on the stack and let the read/write operations copy it from/to the page buffer later. Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Cc: stable@vger.kernel.org Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-2-frieder.schrempf@kontron.de
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass1-1/+1
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-30mtd: spi-nand: Fix not calling dev_err with a deviceSean Anderson1-4/+4
Get it from spinand->slave->dev. Another option would be to use spinand_to_mtd(spinand)->dev, but this is what the existing code uses. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-07-20mtd: spinand: micron: Add new Micron SPI NAND devices with multiple diesShivamurthy Shastri1-0/+55
Add device table for new Micron SPI NAND devices, which have multiple dies. Also, enable support to select the dies. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-20mtd: spinand: micron: Add M70A series Micron SPI NAND devicesShivamurthy Shastri1-0/+20
Add device table for M70A series Micron SPI NAND devices. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-20mtd: spinand: micron: identify SPI NAND device with Continuous Read modeShivamurthy Shastri1-0/+16
Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with the Continuous Read mode. Some of the Micron SPI NAND devices have the "Continuous Read" feature enabled by default, which does not fit the subsystem needs. In this mode, the READ CACHE command doesn't require the starting column address. The device always output the data starting from the first column of the cache register, and once the end of the cache register reached, the data output continues through the next page. With the continuous read mode, it is possible to read out the entire block using a single READ command, and once the end of the block reached, the output pins become High-Z state. However, during this mode the read command doesn't output the OOB area. Hence, we disable the feature at probe time. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-20mtd: spinand: micron: Add new Micron SPI NAND devicesShivamurthy Shastri1-0/+30
Add device table for M79A and M78A series Micron SPI NAND devices. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-20mtd: spinand: micron: Describe the SPI NAND device MT29F2G01ABAGDShivamurthy Shastri1-0/+1
Add the SPI NAND device MT29F2G01ABAGD series number, size and voltage details as a comment. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-20mtd: spinand: micron: Generalize the OOB layout structure and function namesShivamurthy Shastri1-14/+14
In order to add new Micron SPI NAND devices, we generalized the OOB layout structure and function names. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-28mtd: spinand: toshiba: Support for new Kioxia Serial NANDYoshio Furuyama1-16/+103
Add support for new Kioxia products. The new Kioxia products support program load x4 command, and have HOLD_D bit which is equivalent to QE bit. Signed-off-by: Yoshio Furuyama <ytc-mb-yfuruyama7@kioxia.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/aa69e455beedc5ce0d7141359b9364ed8aec9e65.1584949601.git.ytc-mb-yfuruyama7@kioxia.com Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-28mtd: spinand: toshiba: Rename function name to change suffix and prefix (8Gbit)Yoshio Furuyama1-27/+27
The suffix was changed from "G" to "J" to classify between 1st generation and 2nd generation serial NAND devices (which now belong to the Kioxia brand). As reference that's 1st generation device of 1Gbit product is "TC58CVG0S3HRAIG" 2nd generation device of 1Gbit product is "TC58CVG0S3HRAIJ". The 8Gbit type "TH58CxG3S0HRAIJ" is new to Kioxia's serial NAND lineup and the prefix was changed from "TC58" to "TH58". Thus the functions were renamed from tc58cxgxsx_*() to tx58cxgxsxraix_*(). Signed-off-by: Yoshio Furuyama <ytc-mb-yfuruyama7@kioxia.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/0dedd9869569a17625822dba87878254d253ba0e.1584949601.git.ytc-mb-yfuruyama7@kioxia.com Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass3-0/+3
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop linux/bug.h from common headerSimon Glass3-0/+3
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-29mtd: nand: spi: add support for Toshiba TC58CVG2S0HRAIJRobert Marko1-0/+10
Toshiba recently launched new revisions of their serial SLC NAND series. TC58CVG2S0HRAIJ is a refresh of previous series with minor improvements. Basic parameters are same so lets add support for this new revision. Datasheet: https://business.kioxia.com/info/docget.jsp?did=58601&prodName=TC58CVG2S0HRAIJ Signed-off-by: Robert Marko <robert.marko@sartura.hr> Tested-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-29mtd: spi-nand: Import Toshiba SPI-NAND supportRobert Marko3-1/+193
Linux has good support for Toshiba SPI-NAND, so lets import it. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Tested-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-02-05dm: core: Create a new header file for 'compat' featuresSimon Glass5-0/+5
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: core: Require users of devres to include the headerSimon Glass1-0/+1
At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-02-05mtd: Rename free() to rfree()Simon Glass5-5/+5
This function name conflicts with our desire to #define free() to something else on sandbox. Since it deals with resources, rename it to rfree(). Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-27mtd: spinand: winbond: Add support for W25N01GVRobert Marko1-0/+8
Linux has supported W25N01GV for a long time, so lets import it. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-12-03mtd: rename CONFIG_MTD -> CONFIG_DM_MTDMiquel Raynal1-1/+1
CONFIG_MTD must be reserved for the MTD core. Like any other subsystem, prefix the symbol by DM when it comes to DM support. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com> [trini: Add Kconfig files] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-04-12mtd: spinand: Sync GigaDevice GD5F1GQ4UExxG with latest Linux versionStefan Roese1-32/+47
This patch sync's the U-Boot SPI NAND GigaDevice GD5F1GQ4UExxG support with the latest Linux version (v5.0-rc3) plus the chip supported posted on the MTD list. Only the currently in U-Boot available chip is supported with this sync. The changes for the GD5F1GQ4UExxG are: - Name of NAND device changed to better reflect the real part - OOB layout changed to only reserve 1 byte for BBT - Use ECC caps 8bits/512bytes instead of 8bits/2048bytes - Enhanced ecc_get_status() function to determine and report a more fine grained bit error status Signed-off-by: Stefan Roese <sr@denx.de> Cc: Boris Brezillon <bbrezillon@kernel.org> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com>
2018-10-04mtd: nand: spi: Add Gigadevice SPI NAND supportStefan Roese3-1/+137
This patch adds support for Gigadevices SPI NAND device to the new SPI NAND infrastructure in U-Boot. Currently only the 128MiB GD5F1GQ4UC device is supported. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Boris Brezillon <boris.brezillon@bootlin.com> Cc: Jagan Teki <jagan@openedev.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com>
2018-09-20mtd: spinand: Add initial support for the MX35LF2GE4AB chipMiquel Raynal1-6/+14
Add support for the MX35LF2GE4AB chip, which is similar to its cousin MX35LF1GE4AB, with two planes instead of one. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com>
2018-09-20mtd: spinand: Add initial support for the MX35LF1GE4AB chipBoris Brezillon3-1/+140
Add minimal support for the MX35LF1GE4AB SPI NAND chip. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com>
2018-09-20mtd: spinand: Add initial support for Winbond W25M02GVFrieder Schrempf3-1/+145
Add support for the W25M02GV chip. Signed-off-by: Frieder Schrempf <frieder.schrempf@exceet.de> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com>
2018-09-20mtd: spinand: Add initial support for Micron MT29F2G01ABAGDPeter Pan3-1/+153
Add a basic driver for Micron SPI NANDs. Only one device is supported right now, but the driver will be extended to support more devices afterwards. Signed-off-by: Peter Pan <peterpandong@micron.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com>
2018-09-20mtd: nand: Add core infrastructure to support SPI NANDsPeter Pan3-0/+1246
Add a SPI NAND framework based on the generic NAND framework and the spi-mem infrastructure. In its current state, this framework supports the following features: - single/dual/quad IO modes - on-die ECC Signed-off-by: Peter Pan <peterpandong@micron.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com>
generated by cgit v1.1 at 2024-08-14 08:06:43 +0000