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2020-10-30Merge tag 'dm-pull-30oct20' of ↵Tom Rini1-5/+2
https://gitlab.denx.de/u-boot/custodians/u-boot-dm of-platdata and dtoc improvements sandbox SPL tests binman support for compressed sections
2020-10-29dm: Use driver_info index instead of pointerSimon Glass1-5/+2
At present we use a 'node' pointer in the of-platadata phandle_n_arg structs. This is a pointer to the struct driver_info for a particular device, and we can use it to obtain the struct udevice pointer itself. Since we don't know the struct udevice pointer until it is allocated in memory, we have to fix up the phandle_n_arg.node at runtime. This is annoying since it requires that SPL's data is writable and adds a small amount of extra (generated) code in the dm_populate_phandle_data() function. Now that we can find a driver_info by its index, it is easier to put the index in the phandle_n_arg structures. Update dtoc to do this, add a new device_get_by_driver_info_idx() to look up a device by drive_info index and update the tests to match. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-29mmc: zynq_sdhci: Extend UHS timings till hs200Ashok Reddy Soma1-1/+1
Fix the condition to set UHS timings for speeds upto HS200. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-27mmc: zynq_sdhci: Add clock phase delays for VersalAshok Reddy Soma1-4/+156
Define default values for input and output clock phase delays for Versal. Also define functions for setting tapdelays based on these clock phase delays. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-27mmc: zynq_sdhci: Set tapdelays based on clk phase delaysAshok Reddy Soma1-5/+123
Define and use functions for setting input and output tapdelays based on clk phase delays. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-27mmc: zynq_sdhci: Read clock phase delays from dtMichal Simek1-0/+85
Define input and output clock phase delays with pre-defined values. Define arasan_sdhci_clk_data type structure and add it to priv structure and store these clock phase delays in it. Read input and output clock phase delays from dt. If these values are not passed through dt, use pre-defined values. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-27mmc: zynq_sdhci: Move macro to the topMichal Simek1-2/+2
Just group macros below headers. Other patches will be using this location too. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-27mmc: Define timing macro'sAshok Reddy Soma1-13/+11
Define timing macro's for all the available speeds of mmc. This is done similar to linux. Replace speed macro's used with these new timing macro's wherever applicable. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-10-27Revert "mmc: zynq: parse dt when probing"Ashok Reddy Soma2-1/+7
This reverts commit 942b5fc03218d1c94468fc658e7dec65dabcc830. This is partial revert of the above commit. mmc_of_parse() is reading no-1-8-v from device tree and if set, it is clearing the UHS speed capabilities of cfg->host_caps. cfg->host_caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400 | MMC_MODE_HS400_ES); This is still missing to clear UHS speeds like SDHCI_SUPPORT_SDR104, SDHCI_SUPPORT_SDR50 and SDHCI_SUPPORT_DDR50. Even if we clear the flags SDHCI_SUPPORT_XXX in mmc_of_parse(), these speed flags are getting set again in cfg->host_caps in sdhci_setup_cfg(). The reason for this is, SDHCI_SUPPORT_XXX flags are cleared only if controller is not capable of supporting MMC_VDD_165_195 volts. if (caps & SDHCI_CAN_VDD_180) cfg->voltages |= MMC_VDD_165_195; if (!(cfg->voltages & MMC_VDD_165_195)) caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); It means "no-1-8-v", which is read from DT is not coming in to effect. So it is better we keep the host quirks(SDHCI_QUIRK_NO_1_8_V) to clear UHS speeds based on no-1-8-v from device tree. Hence revert the functionality related to no-1-8-v only, rest is fine in the patch. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-10-22mmc: mtk-sd: change some dev_err into dev_dbgFabien Parent1-3/+3
dev_err has been used for debugging and a few dev_err message are printed for normal code execution. Make them dev_dbg instead. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-10-22mmc: Fix comment typoNaoki Hayama1-1/+1
%s/occured/occurred/ Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
2020-10-21mmc: stm32_sdmmc2: Use mmc_of_parse() to read host capabilitiesAlexandru Gagniuc1-16/+2
mmc_of_parse() can populate the 'f_max' and 'host_caps' fields of struct mmc_config from devicetree. The same logic is duplicated in stm32_sdmmc2_probe(). Use mmc_of_parse(), which is more generic. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-21mmc: mmc_of_parse: Enable 52 MHz support with "cap-mmc-highspeed"Alexandru Gagniuc1-1/+1
"cap-mmc-highspeed" enables support for 26 MHz MMC, but there is no additional flag to enable 52 MHz MMC. In Linux. "cap-mmc-highspeed" is used for MMC HS at both 26MHz and 52MHz. Use the same approach and enable MMC_CAP(MMC_HS_52) host capability when "cap-mmc-highspeed" is found in the devicetree. In the event an MMC card doesn't support 52 MHz, it will be clocked at a speed based on its EXT CSD, even on 52 MHz host controllers Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-16mmc: octeontx_hsmmc.c: Remove test debug messageStefan Roese1-1/+0
Remove a left-over debug test message from the Octeon TX / TX2 MMC driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
2020-10-15Merge tag 'mmc-2020-10-14' of ↵Tom Rini9-229/+482
https://gitlab.denx.de/u-boot/custodians/u-boot-mmc - fsl_esdhc_imx cleanup - not send cm13 if send_status is 0. - Add reinit API - Add mmc HS400 for fsl_esdhc - Several cleanup for fsl_esdhc - Add ADMA2 for sdhci
2020-10-14mmc: remove duplicate mmc_get_env_dev() implementationsDavid Woodhouse1-0/+9
Since it's so trivial I could just about tolerate this when there were only two copies of it. But now there are about to be three. Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2020-10-14mmc: fsl_esdhc: add ADMA2 supportMichael Walle2-5/+53
Newer eSDHC controllers support ADMA2 descriptor tables which support 64bit DMA addresses. One notable user of addresses in the upper memory segment is the EFI loader. If support is enabled, but the controller doesn't support ADMA2, we will fall back to SDMA (and thus 32 bit DMA addresses only). Signed-off-by: Michael Walle <michael@walle.cc>
2020-10-14mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()Michael Walle1-73/+65
Make the code cleaner and drop the old-style #ifdef constructs where it is possible. Signed-off-by: Michael Walle <michael@walle.cc>
2020-10-12mmc: fsl_esdhc_imx: replace all readl/writel to esdhc_read32/esdhc_write32Haibo Chen1-32/+32
Currently, readl/writel and esdhc_read32/esdhc_write32 are used. To align the usage, change to only use esdhc_read32/esdhc_write32. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2020-10-12mmc: do not check argument of free() beforehandHeinrich Schuchardt1-2/+1
free() checks if its argument in NULL. No need to check it twice. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-12mmc: sdhci: move the ADMA2 table handling into own moduleMichael Walle4-55/+87
There are other (non-SDHCI) controllers which supports ADMA2 descriptor tables, namely the Freescale eSDHC. Instead of copying the code, move it into an own module. Signed-off-by: Michael Walle <michael@walle.cc>
2020-10-12mmc: fsl_esdhc: simplify esdhc_setup_data()Michael Walle1-27/+42
First, we need the waterlevel setting for PIO mode only. Secondy, both DMA setup code is identical for both directions, except for the data pointer. Thus, unify them. Signed-off-by: Michael Walle <michael@walle.cc>
2020-10-12mmc: fsl_esdhc: use dma-mapping APIMichael Walle1-35/+14
Use the dma_{map,unmap}_single() calls. These will take care of the flushing and invalidation of caches. Signed-off-by: Michael Walle <michael@walle.cc>
2020-10-12mmc: fsl_esdhc: simplify 64bit check for SDMA transfersMichael Walle1-23/+6
SDMA can only do DMA with 32 bit addresses. This is true for all architectures (just doesn't apply to 32 bit ones). Simplify the code and remove unnecessary CONFIG_FSL_LAYERSCAPE. Also make the error message more concise. Signed-off-by: Michael Walle <michael@walle.cc>
2020-10-12mmc: fsl_esdhc_imx: remove the 1ms delay before sending commandHaibo Chen1-7/+0
This 1ms delay before sending command already exist from the beginning of the fsl_esdhc driver added in year 2008. Now this driver has been split for two files: fsl_esdhc.c and fsl_esdhc_imx.c. fsl_esdhc_imx.c only for i.MX series. i.MX series esdhc/usdhc do not need this 1ms delay before sending any command. So remove this 1ms, this will save a lot time if handling a large mmc data. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2020-10-12mmc: do not send cmd13 if the parameter 'send_status' is 0 for __mmc_switchHaibo Chen1-1/+3
According to the code logic in __mmc_switch, if the parameter 'send_status' is zero, no need to send cmd13, just wait the stated timeout time, then can return directly. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2020-10-12mmc: fsl_esdhc: fix eMMC HS400 stability issueYangbo Lu1-1/+4
There was a fix-up for eMMC HS400 stability issue in Linux. Patch link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/ commit/?id=58d0bf843b49fa99588ac9f85178bd8dfd651b53 Description: Currently only LX2160A eSDHC supports eMMC HS400. According to a large number of tests, eMMC HS400 failed to work at 150MHz, and for a few boards failed to work at 175MHz. But eMMC HS400 worked fine on 200MHz. We hadn't found the root cause but setting eSDHC_DLLCFG0[DLL_FREQ_SEL] = 0 using slow delay chain seemed to resovle this issue. Let's use this as fixup for now. Introduce the fix-up in u-boot since the issue could be reproduced in u-boot too. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12mmc: fsl_esdhc: fix mmc->clock with actual clockYangbo Lu1-0/+3
Fix mmc->clock with actual clock which is divided by the controller, and record it with priv->clock which was removed accidentally. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12mmc: fsl_esdhc: support eMMC HS400 modeYangbo Lu1-34/+86
The process for eMMC HS400 mode for eSDHC is, 1. Perform the Tuning Process at the HS400 target operating frequency. Latched the clock division value. 2. if read transaction, then set the SDTIMNGCTL[FLW_CTL_BG]. 3. Switch to High Speed mode and then set the card clock frequency to a value not greater than 52Mhz 4. Clear TBCTL[TB_EN],tuning block enable bit. 5. Change to 8 bit DDR Mode 6. Switch the card to HS400 mode. 7. Set TBCTL[TB_EN], tuning block enable bit. 8. Clear SYSCTL[SDCLKEN] 9. Wait for PRSSTAT[SDSTB] to be set 10. Change the clock division to latched value.Set TBCTL[HS 400 mode] and Set SDCLKCTL[CMD_CLK_CTRL] 11. Set SYSCTL[SDCLKEN] 12. Wait for PRSSTAT[SDSTB] to be set 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 14. Wait for delay chain to lock. 15. Set TBCTL[HS400_WNDW_ADJUST] 16. Again clear SYSCTL[SDCLKEN] 17. Wait for PRSSTAT[SDSTB] to be set 18. Set ESDHCCTL[FAF] 19. Wait for ESDHCCTL[FAF] to be cleared 20. Set SYSCTL[SDCLKEN] 21. Wait for PRSSTAT[SDSTB] to be set. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12mmc: add a mmc_hs400_prepare_ddr() interfaceYangbo Lu2-0/+19
Add a mmc_hs400_prepare_ddr() interface for controllers which needs preparation before switching to DDR mode for HS400 mode. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12mmc: add a hs400_tuning flagYangbo Lu1-0/+2
Some controllers may have difference between HS200 tuning and HS400 tuning, such as different registers setting, different procedure, or different errata. This patch is to add a hs400_tuning flag to identify the tuning for HS400 mode. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12mmc: fsl_esdhc: clean TBCTL[TB_EN] manually during initYangbo Lu1-0/+3
Clean TBCTL[TB_EN] manually during init since it is not able to be reset by reset all operation. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12mmc: fsl_esdhc: support tuning for eMMC HS200Yangbo Lu1-3/+103
Support tuning process for eMMC HS200 for eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12mmc: fsl_esdhc: add a reinit() callbackYangbo Lu1-0/+9
Add a reinit() callback for mmc rescan. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-12mmc: add a reinit() APIYangbo Lu2-2/+21
For DM_MMC, the controller re-initialization is needed to clear old configuration for mmc rescan. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-05Merge branch 'next'Tom Rini4-32/+41
Bring in the assorted changes that have been staged in the 'next' branch prior to release. Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-05Merge tag 'u-boot-atmel-2021.01-a' of ↵Tom Rini1-3/+10
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel into next First set of u-boot-atmel features for 2021.01 cycle: This feature set includes a new CPU driver for at91 family, new driver for PIT64B hardware timer, support for new at91 family SoC named sama7g5 which adds: clock support, including conversion of the clock tree to CCF; SoC support in mach-at91, pinctrl and mmc drivers update. The feature set also includes updates for mmc driver and some other minor fixes and features regarding building without the old Atmel PIT and the possibility to read a secondary MAC address from a second i2c EEPROM.
2020-09-30mmc: mtk-sd: Fix not calling dev_err with a deviceSean Anderson1-11/+13
This adds a udevice parameter to get_best_delay and msdc_set_mclk so they can call dev_err properly. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30mmc: bcm2835-host: Fix not calling dev_dbg with a deviceSean Anderson1-17/+17
dev needs to be qualified as a member of host. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-25mmc: atmel-sdhci: use mmc_of_parse to get the DT propertiesEugen Hristev1-0/+4
Call mmc_of_parse at probe time to fetch all the host properties from the DT. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-09-25mmc: atmel-sdhci: enable the required generic clockEugen Hristev1-0/+4
The second clock of the IP block (the generic clock), must be explicitly enabled. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Peng Fan <pengfan@nxp.com>
2020-09-25mmc: atmel-sdhci: do not check clk_set_rate return valueEugen Hristev1-3/+1
clk_set_rate will return rate in case of success and zero in case of error, however it can also return -ev, but it's an ulong function. To avoid any issues, disregard the return value of this call. In case this call actually fails, nothing much we can do anyway, but we can at least try with the previous values (or DT assigned-clocks) Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-09-25mmc: atmel-sdhci: add sama7g5-sdhci compatibility stringEugen Hristev1-0/+1
Add new compatibility string for matching sama7g5 product. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-09-23mmc: zynq: Fix incorrect indentationMichal Simek1-1/+1
Trivial fix. Fixes: d1f4e39d58db ("mmc: zynq_sdhci: Add support for SD3.0" Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23mmc: pic32: Refresh PIC32 MMC driverJohn Robertson1-36/+50
The existing driver is not compatible with the Driver Model. This patch makes the necessary changes while also removing obsolescent calls/properties as follows: - fdtdec_* calls replaced with dev_read_* equivalents; - 'clock-freq-min-max' property replaced by querying the frequency of the source clock 'base_clk'; - The card detect erratum workaround is applied during probe rather than overriding get_cd. The card detect workaround (Microchip ref. DS80000736E, erratum #15) is not always needed and can be disabled using a vendor specific DT property. Signed-off-by: John Robertson <john.robertson@simiatec.com>
2020-09-17mmc: fsl_esdhc_imx: check the clock stable status after config the clock rate.Haibo Chen1-1/+6
Currently, after config the clock rate, delay 10ms, this is quite a rough method. Check the clock stable status in the present status register is enough. Tested-by: Ji Luo <ji.luo@nxp.com> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2020-09-15mmc: xenon_sdhci: Add missing common host capabilitiesAndre Heider1-14/+4
Use mmc_of_parse() to set the common host properties. That includes "bus-width", so parsing it can be removed from the driver. But more importantly, "non-removable" is now respected, which fixes the usage of eMMC. Signed-off-by: Andre Heider <a.heider@gmail.com> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Tested-by: Marek Behún <marek.behun@nic.cz>
2020-09-15mmc: msm_sdhci: Use mmc_of_parse for setting host_capsManivannan Sadhasivam1-0/+4
Since the introduction of 'get_cd' callback in sdhci core, dragonboard410c's MMC interface is broken. It turns out that 'get_cd' callback checks for the host_caps for validating the chip select. And since the msm_sdhci driver is not parsing the host_caps from DT, not all of the cababilities are parsed properly. This results in the MMC interfaces to be broken. Hence, fix this by adding a call to 'mmc_of_parse' during driver probe. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Tested-by: Aníbal Limón <anibal.limon@linaro.org> Reviewed-By: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-08-31mmc: xenon: set signal voltage and max base clockEvan Wang1-1/+78
- The SDIO signal voltage and max base clock frequency setting are missing in driver, which causes SDIO not working. - The patch adds SDIO signal voltage switch support, which is based on regulator-gpio of vqmmc-supply, and sets the max base clock frequency. - Fix the zero clock value in call to sdhci_setup_cfg() function. Change-Id: I79c8860c65b8db166f4f70db56ede4097f71f1fa Signed-off-by: Evan Wang <xswang@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53589 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: Hua Jing <jinghua@marvell.com> [pali: Amended fixup patch] Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-25mmc: Add MMC controller driver for OcteonTX / TX2Suneel Garapati4-0/+4114
Adds support for MMC controllers found on OcteonTX or OcteonTX2 SoC platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Peng Fan <peng.fan@nxp.com>
generated by cgit v1.1 at 2024-09-03 09:21:31 +0000