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2021-01-31mmc: tmio: sdhi: Configure internal DMA bus widthMarek Vasut3-0/+8
The R-Car3 SDHI should set these two bits in DMA_MODE register according to the specification, to indicate 64bit bus width. No other bus width options are permitted and the default value is 0, which is incorrect. Set the bits accordingly. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-01-27mmc: pci_mmc: Set the removable flagSimon Glass1-0/+8
Set this flag so that it is available to those looking at the device. For non-removable devices there is no need to check for insertion/removable since the media can never change. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-01-27mmc: pci_mmc: Only generate ACPI code for the SD cardSimon Glass1-1/+10
At present if an eMMC part is in the system, the ACPI table generated will include information about that, as well as the SD card. We only need to include the SD card, since it has a card-detect GPIO. Use a different compatible string for each option, and add code only for the SD card. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-01-27arm: mvebu: Espressobin: Disable slot when emmc is not presentPali Rohár1-0/+19
This change extends previous commit 061c6d1b238a ("arm: mvebu: Espressobin: Detect presence of emmc at runtime") and when emmc is not present then emmc is removed from U-Boot DM and corresponding slot is disabled. Therefore on Espressobin board without soldered emmc, state of emmc hw should be same as if emmc was disabled in DTS. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-01-25Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiWIP/25Jan2021Tom Rini1-67/+29
- New Allwinner H616 SoC support (sans Ethernet & USB) - H6 DT update - Tanix TX6 TV box support - OrangePi 3 support - OrangePi Zero2 (H616) support
2021-01-25mmc: sunxi: Refactor mod clock register offsetAndre Przywara1-61/+23
So far the only difference between the various Allwinner MMC controller we are concerned about is the mod clock register offset. This is actually not directly related to the MMC controller IP, but an integration choice, dependent on the SoC this appears in. To avoid becoming trapped with some compatible fallback strings, let's remove the whole struct sunxi_mmc_variant, and replace this with a SoC based choice, which we can derive from the CONFIG_MACH_SUNx_y symbols. This will later simplify H616 support. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-01-25mmc: sunxi: Replace H6 ifdefs with H6 gen macroJernej Skrabec1-6/+6
It turns out that several SoCs share same mmc configuration as H6. In order to lower ifdef clutter replace H6 specific macro with common one. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-25Merge tag 'mips-pull-2021-01-24' of ↵Tom Rini1-12/+124
https://gitlab.denx.de/u-boot/custodians/u-boot-mips - MIPS: add support for Mediatek MT7620 SoCs
2021-01-25Merge tag 'u-boot-imx-20210125' of ↵Tom Rini1-0/+2
https://gitlab.denx.de/u-boot/custodians/u-boot-imx Changes for 2020.04 ------------------- - new board: Phytec phyCORE-i.MX8MP i.MX8MN Beacon EmbeddedWorks devkit - Fixes: several nanbcb fixes fix for imx8mm_beacon - further switch to distro boot commands - DM: DM Ether for MX6UL CI: https://gitlab.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/6013
2021-01-24mmc: mtk-sd: assign plat->cfg.f_max with a correct valueWeijie Gao1-0/+2
Currently this driver does not set the value of plat->cfg.f_max, which results in that MMC framework will always run at the lowest frequency. This patch sets plat->cfg.f_max to the maximum allowed frequency, which equals to the source clock frequency. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24mmc: mtk-sd: add pad control settings for MediaTek MT7620/MT76x8 SoCsWeijie Gao1-3/+118
The driver is missing pad control settings (pad delay and pad conf) for the mt7620 and mt76x8. Although mt76x8 still works well, mt7620 will encounter CRC error on data transfers. This patch adds default pad control settings for mt7620_compat. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24mmc: mtk-sd: fix sclk cycles shift valueWeijie Gao1-9/+4
It turns out that the sclk cycles used by mt7620/mt7628 is the same as other chips (20 bits, 1048576), not 65536. This patch removes sclk_cycle_shift from dev_comp, and uses a macro with a value 20 instead. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-23mmc: fsl_esdhc_imx.c: fix compiler warningHeiko Schocher1-0/+2
prevent unsued variable compiler warning if DM_REGULATOR is not set. Signed-off-by: Heiko Schocher <hs@denx.de>
2021-01-22Merge https://gitlab.denx.de/u-boot/custodians/u-boot-samsung.gitTom Rini1-56/+0
2021-01-20mmc: xenon_sdhci: Remove duplicated macrosMichal Simek1-12/+0
There is no need to define the same macros in drivers. All macros have been added by commit 17a42abb40dd ("mmc: Define timing macro's"). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-01-18mmc: fsl_esdhc_spl: remove superfluous free()Heinrich Schuchardt1-3/+0
Freeing a buffer before calling hang() is superfluous. Removing the call reduces the SPL size. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-01-18mmc: Only retrieve cd pin when GPIO is enabledHarm Berntsen1-2/+4
The driver only needs to retrieve the pin for the ACPI info. The driver itself works without depending on GPIO. Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com> CC: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15mmc: dwmmc: socfpga: Add ATF support for MMC driverChee Hong Ang1-0/+14
In non-secure mode (EL2), MMC driver calls the SMC/PSCI services provided by ATF to set SDMMC's DRVSEL and SMPLSEL. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-01-15mmc: dwmmc: Change designware MMC 'clksel' callback function to return statusSiew Chin Lim5-6/+19
Change 'clksel' callback function to allow the code to return a status. This patch is a preparation for enabling Arm-Trusted-Firmware (ATF) in Intel SoC FPGA. This patch does not change functionality. When using Arm-Trusted-Firmware (ATF) in Intel SoC FPGA, the MMC clock related register is secure register which is required to be written via SMC/PCSI call. It is possible that U-Boot fail to write the register if there is unexpected error between U-Boot and ATF. As a result, there maybe signal integrity on MMC connection due to clock. So, the code should reports error to user when 'clksel' fail. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-01-13mmc: stm32_sdmmc2: migrate trace to dev and log macroPatrick Delaunay1-40/+44
Define LOG_CATEGORY, use dev_ macro when it is possible. Remove the "%s:" __func__ header as it is managed by dev macro (dev->name is displayed) or log macro (CONFIG_LOGF_FUNC). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2021-01-13mmc: exynos_dw_mmc: remove unused functionJaehoon Chung1-56/+0
Remove unused function in exynos_dw_mmc.c. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2021-01-05Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextWIP/05Jan2021-nextTom Rini6-25/+35
Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
2021-01-05Merge tag 'v2021.01-rc5' into nextTom Rini4-11/+43
Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-05dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIASSimon Glass3-4/+4
We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05dm: core: Access device ofnode through functionsSimon Glass1-10/+13
At present ofnode is present in the device even if it is never used. With of-platdata this field is not used, so can be removed. In preparation for this, change the access to go through inline functions. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05dm: core: Use dev_has_ofnode() instead of dev_of_valid()Simon Glass1-1/+1
We have two functions which do the same thing. Standardise on dev_has_ofnode() since there is no such thing as an 'invalid' ofnode in normal operation: it is either null or missing. Also move the functions into one place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2021-01-05dm: core: Rename dev_has_of_node() to dev_has_ofnode()Simon Glass1-1/+1
We use 'ofnode' rather than 'of_node' in U-Boot. Rename this function to fit. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05dm: Use access methods for dev/uclass private dataSimon Glass3-9/+16
Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
2020-12-22spi: spi-uclass: Fix spi_claim_bus() speed/mode setup logicOvidiu Panait1-1/+0
Currently, when different spi slaves claim the bus consecutively using spi_claim_bus(), spi_set_speed_mode() will only be executed on the first two calls, leaving the bus in a bad state starting with the third call. This patch drops spi_slave->speed member and adds caching of bus speed/mode in dm_spi_bus struct. It also updates spi_claim_bus() to call spi_set_speed_mode() if either speed or mode is different from what the bus is currently configured for. Current behavior is to only take into account the speed, but not the mode, which seems wrong. Fixes: 60e2809a848 ("dm: spi: Avoid setting the speed with every transfer") Reviewed-by: Simon Glass <sjg@chromium.org> Reported-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reported-by: Moshe, Yaniv <yanivmo@amazon.com> Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2020-12-18octeon: Don't attempt to set the sequence numberSimon Glass1-2/+0
Several Octeon drivers operate by setting the sequence number of their device. This should not be needed with the new sequence number setup. Also it is not permitted. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-18dm: Avoid accessing seq directlySimon Glass1-2/+2
At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass3-16/+16
Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass22-44/+44
This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass46-131/+131
Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass48-52/+52
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass48-91/+91
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-11Merge tag 'u-boot-atmel-fixes-2021.01-b' of ↵WIP/11Dec2020Tom Rini1-1/+2
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel Second set of u-boot-atmel fixes for 2021.01 cycle This set includes very important fixes for: MMC booting on several boards, drive strength on sam9x60ek mmc lines, compile issues for timer.c old driver, removal of unwanted access to sam9x60 bit for oscillator bypass mode, and eeproms read on sama5d2_icp.
2020-12-09Merge tag 'u-boot-stm32-20201209' of ↵WIP/09Dec2020Tom Rini2-2/+2
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Manage CONFIG_ENV_EXT4_DEVICE_AND_PART in stm32mp1 board - Update ARM STI and ARM STM STM32MP Arch maintainers emails - Enable internal pull-ups for SDMMC1 on DHCOM SoM
2020-12-09treewide: Update email address Patrick Delaunay and Patrice ChotardPatrice Chotard2-2/+2
Update Patrick and my email address with the one dedicated to upstream activities. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-12-06mmc: fsl_esdhc_imx: optimize the timing settingHaibo Chen1-8/+24
For imx usdhc/esdhc, once set the DDR_EN, enable the DDR mode, the card clock will be divied by 2 automatically by the host. So need to first config the DDR_EN correctly, then update the card clock. This will make sure the actual card clock is as our expected. IC also suggest config the DDR_EN firstly, then config the clock divider. For HS400/HS400ES mode, need to config the strobe dll, this need to based on the correct target clock rate, so need to do this after clock rate is update. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-12-06mmc: fsl_esdhc_imx: add wait_dat0() supportHaibo Chen1-0/+15
Add wait_dat0() support, upper layer will use this callback. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-11-28mmc: check a return value about regulator's always-onJaehoon Chung1-2/+2
Regulator can be set to "always-on". It's not error about enable/disable. It needs to check about its condition. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-11-28mmc: display an error number to debugJaehoon Chung1-5/+5
It's useful to know an error number when it's debugging. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-11-28mmc: fsl_esdhc: make sure delay chain locked for HS400Yangbo Lu1-3/+25
For eMMC HS400 mode, the DLL reset is a required step for mmc rescan. This step has not been documented in reference manual, but the RM will be fixed sooner or later. In previous commit to support eMMC HS400, db8f936 mmc: fsl_esdhc: support eMMC HS400 mode the steps to configure DLL could be found in commit message, 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 14. Wait for delay chain to lock. these would be fixed as, 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 13.1 Write DLLCFG0[DLL_RESET] to 1 and wait for 1us, then write DLLCFG0[DLL_RESET] 14. Wait for delay chain to lock. This patch is to add the step of DLL reset, and make sure delay chain locked for HS400. Fixes: db8f93672b42 ("mmc: fsl_esdhc: support eMMC HS400 mode") Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-11-28mmc: fsl_esdhc: set sysctl register for clock initializationYangbo Lu1-1/+1
The initial clock setting should be through sysctl register only, while the mmc_set_clock() will call mmc_set_ios() introduce other configurations like bus width, mode, and so on. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-11-28mmc: Add some helper functions for retrying on errorSean Anderson1-83/+58
All of the existing quirks add retries to various calls of mmc_send_cmd. mmc_send_cmd_quirks is a helper function to do this retrying behavior. It checks if quirks mode is enabled, and if a specific quirk is activated it retries on error. This also adds mmc_send_cmd_retry, which retries on error every time (instead of if a quirk is activated). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-11-26mmc: atmel-sdhci: fix the clk_enable call in case of no opsEugen Hristev1-1/+2
If the clock driver does not offer a clk_enable ops, then the system will return -ENOSYS. The clk_enable works with CCF (common clock framework). Some clocks in some cases (like the generic clock for some products: sama5d2) do not have the clk_enable primitive, and in this case probing of the driver will fail. This patch changes the behavior to return an error in case there is really an error, and not a missing primitive. If the clock driver does not have an enable primitive, most likely clocks are always enabled or enabled in the set_rate primitives. Fixes: 81f16438d4 ("mmc: atmel-sdhci: enable the required generic clock") Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-11-12mmc: meson-gx: change clock phase value on SM1 SoCsNeil Armstrong2-4/+28
Amlogic SM1 SoCs doesn't work over 50MHz. When phase sets to 270', it's working fine over 50MHz on Amlogic SM1 SoCs. Since Other Amlogic SoCs doens't report an issue, phase value is using to 180' by default. To distinguish which value is used adds an u-boot only sm1 compatible. In future, it needs to find what value is a proper about each SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Anand Moon <linux.amoon@gmail.com>
2020-11-12mmc: meson-gx: move arch header to local headerNeil Armstrong2-1/+90
Move the asm/arch-meson/sd_emmc.h to a local meson_gx_mmc.h, remove the useless if/then and fix the meson_gx_mmc.c include. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-30Merge tag 'dm-pull-30oct20' of ↵Tom Rini1-5/+2
https://gitlab.denx.de/u-boot/custodians/u-boot-dm of-platdata and dtoc improvements sandbox SPL tests binman support for compressed sections
generated by cgit v1.1 at 2024-07-14 14:04:12 +0000