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2018-11-14test: dm: pci: Add cases for finding next PCI capability APIsBin Meng1-0/+9
Add test cases to cover the two newly added PCI APIs: dm_pci_find_next_capability() & dm_pci_find_next_ext_capability(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-14misc: Add IHS FPGA driverMario Six4-0/+926
Add a driver for gdsys IHS (Integrated Hardware Systems) FPGAs, which supports initialization of the FPGA, as well as information gathering. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-11-14misc: Add gdsys_soc driverMario Six4-0/+106
This patch adds a driver for the bus associated with a IHS FPGA. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-11-14misc: Sort Makefile entriesMario Six1-30/+31
Makefile entries should be sorted. Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc> Signed-off-by: Anatolij Gustschin <agust@denx.de>
2018-11-14dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in lists_bind_fdt()Bin Meng1-2/+2
Currently the comments of several APIs (eg: dm_init_and_scan()) say: @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers. The 'Pre-Relocation Support' chapter in doc/driver-model/README.txt documents the same that both device tree properties and driver flag are supported. However the implementation only checks these special device tree properties without checking the driver flag at all. This updates lists_bind_fdt() to consider both scenarios. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Squashed in http://patchwork.ozlabs.org/patch/996473/ : Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-28drivers: cosmetic: Convert SPDX license tags to Linux Kernel stylePatrick Delaunay1-2/+2
Complete in the drivers directory the work started with commit 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style"). Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-25Merge tag 'u-boot-imx-20181025' of git://git.denx.de/u-boot-imxTom Rini4-0/+637
Merged imx8 architecture, fix build for imx8 + warnings
2018-10-22misc: imx8: add scfw api impementationPeng Fan2-1/+368
Add clk/misc/pad/pm/rm scfw api implementaion for different drivers to invoke. The low level code is using misc_call to invoke imx8_scu driver. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2018-10-22misc: add i.MX8 misc driverPeng Fan3-0/+270
Add i.MX8 MISC driver to handle the communication between A35 Core and SCU. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2018-10-09cros_ec: Add support for v3 messages on LPCSimon Glass1-0/+33
At present version 3 messages are only supported on SPI. Add support for using LPC as well, as used on samus. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-09cros_ec: Update cros_ec_read_hash() to specify the imageSimon Glass1-3/+4
Allow selection of which EC image to hash. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-09cros: Update ec_commands to latest versionSimon Glass2-5/+6
This file has changed quite a bit in the last 5 years as the capabilities of the ECs have grown. Sync it up with the copy in coreboot commit b9141f2215. The only change is the addition of EC_VBNV_BLOCK_SIZE_V2. This is needed because U-Boot uses the new v2 vboot API and this is not currently fully supported by Chromium OS firmware. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-09cros: Update cros_ec code to use struct udeviceSimon Glass2-75/+76
At present we pass around a private pointer to specify the cros_ec device. With driver model it makes more sense to pass the device. Update the code to do this. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-09dm: core: Update ofnode to read binman-style flash entrySimon Glass1-16/+17
At present ofnode_read_fmap_entry() reads a flash map entry in a format which is not supported by binman. To allow use to use binman-format descriptions, update this function. Also add a simple test. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-06misc: Add support for the Arm Versatile Express config busLiviu Dudau3-0/+137
Add support for the Arm Versatile Express config bus that is being used for exposing various subsystems via a generic configuration bus. This driver adds support for generating transactions on this configuration bus and can be used by other drivers to abstract the communication with the actual function providers. Signed-off-by: Liviu Dudau <liviu.dudau@foss.arm.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2018-09-29Merge tag 'fsl-qoriq-for-v2018.11-rc1' of git://git.denx.de/u-boot-fsl-qoriqTom Rini1-5/+6
Switch to driver model for eSDHC on Layerscape SoCs including LS1021A, LS1043A, LS1046A, LS1088A, LS2088A. Switch to driver model for SATA on LS1021A and LS1043A. Add support for LS1012AFRWY rev C board. Enable SMMU for LS1043A.
2018-09-28common: Generic loader for file systemTien Fong Chee3-0/+305
This is file system generic loader which can be used to load the file image from the storage into target such as memory. The consumer driver would then use this loader to program whatever, ie. the FPGA device. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-09-27armv8: ls1043a: enable icid setup for qman portalsLaurentiu Tudor1-5/+6
Enable support for ICID setup of qman portals and the required device tree fixups. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-18misc: Add MPC83xx serdes driverMario Six4-0/+425
Add a driver to configure the SerDes (Serializer/Deserializer) lanes on the MPC83xx architecture. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-08-17Convert CONFIG_TWL4030_LED et al to KconfigAdam Ford1-0/+5
This converts the following to Kconfig: CONFIG_TWL4030_LED CONFIG_TWL4030_INPUT This also removes dead references to: CONFIG_TWL4030_KEYPAD Signed-off-by: Adam Ford <aford173@gmail.com>
2018-08-13Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini1-6/+39
2018-08-11misc: Add gdsys_ioep driverMario Six4-0/+353
Add driver for the IHS IO endpoint on IHS FPGAs. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-08-11test: Add tests for misc uclassMario Six2-1/+134
Add a set of tests for the misc uclass. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-11misc: uclass: Add enable/disable functionMario Six1-0/+10
Add generic enable/disable function to the misc uclass. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-08-10armv8: ls1046a: add icid setup for qman portalsLaurentiu Tudor1-4/+39
Add support for ICID setting of qman portals and the required device tree fixups. Also fix an endiness issue in portal setup code. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10misc: fsl_portals: setup QMAN_BAR{E} also on ARM platformsLaurentiu Tudor1-2/+0
QMAN_BAR{E} register setup was disabled on ARM platforms, however the register does need to be set. Enable the code also on ARMs and fix the CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly enabled code works. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-08test: dm: pci: Add cases for finding PCI capability APIsBin Meng1-0/+21
Add several PCI capability and extended capability ID registers in the swap_case driver, so that we can add test case for dm_pci_find_capability() and dm_pci_find_ext_capability(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08pci: sandbox: swap_case: Declare dynamic driver matchingBin Meng1-0/+7
This adds a U_BOOT_PCI_DEVICE() declaration to the swap_case driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08pci: sandbox: swap_case: Preserve space indicator bit in BAR registersBin Meng1-3/+5
With the newly added testing of more than one device, we get: => ut dm pci_swapcase Test: dm_test_pci_swapcase: pci.c test/dm/pci.c:88, dm_test_pci_swapcase(): "tHIS IS A tESt" = ptr: Expected "tHIS IS A tESt", got "this is a test" Test: dm_test_pci_swapcase: pci.c (flat tree) test/dm/pci.c:88, dm_test_pci_swapcase(): "tHIS IS A tESt" = ptr: Expected "tHIS IS A tESt", got "this is a test" Failures: 2 The failure only happens on the 2nd swap_case device on the PCI bus. The case passes on the 1st device. It turns out the swap_case driver does not emulate bit#0 in BAR registers as a read-only bit. This corrects the implementation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-20misc: stm32: Add STM32MP1 supportPatrick Delaunay2-5/+16
Following next kernel rcc bindings, we must use a MFD RCC driver which is able to bind both clock and reset drivers. We can reuse and adapt RCC MFD driver already available for MCU SoCs (F4/F7/H7). Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-07-09dm: core: Update of_read_fmap_entry() for livetreeSimon Glass1-2/+2
Update this function to take an ofnode so that it can work with livetree. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-06-19sandbox: swap_case: Increase number of base address regsSimon Glass1-1/+1
At present the code overruns the bar[] array. Fix this. At the same time, drop the leading / from the "/spl" path so that we can run U-Boot SPL with: spl/u-boot-spl rather than requiring: /path/to/spl/u-boot-spl Reported-by: Coverity (CID: 131199) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-06-05mach-stm32: Enable SPL_RESET_SUPPORT flagPatrice Chotard1-4/+0
Since commit 0e373c0ade8c ("spl: add SPL_RESET_SUPPORT"), reset is supported in SPL, enable this flag for STM32F SoCs family. This allows to remove a specific case in RCC mfd driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26stm32mp1: add FUSE command supportPatrick Delaunay3-0/+126
Add support of fuse command (read/write/program/sense) on bank 0 to access to BSEC SAFMEM (4096 OTP bits). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-08gdsys: drivers: Add gdsys_rxaui_ctrl driverMario Six3-1/+82
Add a driver for RXAUI control on IHS FPGAs. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-08clk: clk_stm32f: Use PLLSAIP as USB 48MHz clockPatrice Chotard1-3/+9
On all STM32F4 and F7 SoCs family (except STM32F429), PLLSAI output P can be used as 48MHz clock source for USB and SDMMC. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Tested By: Bruno Herrera <bruherrera@gmail.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini39-79/+39
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTRTom Rini6-12/+0
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-03-05libfdt: move headers to <linux/libfdt.h> and <linux/libfdt_env.h>Masahiro Yamada1-1/+1
Thomas reported U-Boot failed to build host tools if libfdt-devel package is installed because tools include libfdt headers from /usr/include/ instead of using internal ones. This commit moves the header code: include/libfdt.h -> include/linux/libfdt.h include/libfdt_env.h -> include/linux/libfdt_env.h and replaces include directives: #include <libfdt.h> -> #include <linux/libfdt.h> #include <libfdt_env.h> -> #include <linux/libfdt_env.h> Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-03-01i2c: Added Kconfig support for CONFIG_ZYNQ_GEM_I2C_MAC_OFFSETVipul Kumar1-0/+6
This patch added Kconfig support for CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET and enabled it in respective defconfig. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-02-04misc: ocotp: add i.MX8M supportPeng Fan1-0/+7
i.MX8M OCOTP follow same flow as i.MX6Q, but it has 64 banks and each bank 4 words. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-30x86: qemu: qfw: Implement acpi_get_rsdp_addr()Bin Meng1-0/+8
U-Boot on QEMU does not build ACPI table by ourself, instead it uses the prebuilt ACPI table via the qfw interface. This implements the qfw version of acpi_get_rsdp_addr() for setup_zimage(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-01-12misc: mxc_ocotp: check fuse word before programming on i.MX7ULPPeng Fan1-0/+17
On i.MX7ULP, the fuse words (except bank 0 and 1) only supports to write once, because they use ECC mode. Multiple writes may damage the ECC value and cause a wrong fuse value decoded when reading. This patch adds a checking before the fuse word programming, only can write when the word value is 0. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-01-10drivers/misc: Share qbman init between archsAhmed Mansour2-0/+306
This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-11-29dm: misc: bind STM32F4/F7 clock from rcc MFD driverPatrice Chotard1-5/+37
Like STM32H7, now STM32F4/F7 clock drivers are binded by MFD stm32_rcc driver. This also allows to add reset support to STM32F4/F7 SoCs family. As Reset driver is not part of SPL supported drivers, don't bind it in case of SPL to avoid that stm32_rcc_bind() returns an error. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-06stm32: fix STMicroelectronics copyrightPatrice Chotard1-2/+2
Uniformize STMicroelectronics copyrights headers for STM32 related code. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-04treewide: replace with error() with pr_err()Masahiro Yamada1-14/+14
U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-22dm: misc: add stm32 rcc driverChristophe Kerello3-0/+55
This patch adds the support of reset and clock control block (rcc) found on STM32 SoCs. This driver is similar to a MFD linux driver. This driver supports currently STM32H7 only. STM32F4 and STM32F7 will be migrated to this rcc MFD driver in the future to uniformize all STM32 SoCs already upstreamed. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18rockchip: efuse: change to use dev_read_addr_ptrPhilipp Tomsich1-1/+1
With the dev_read_addr_ptr function available, we can change the efuse driver to use it (and eliminate the explicit type-cast). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-12misc: i2c_eeprom: Add compatible for AT24MAC402Wenyou Yang1-0/+1
Add the new compatible "atmel,24mac402" to accommodate AT24MAC402. The AT24MAC402 is a 2K Serial EEPROM and the 2-Kbit memory array is internally organized as 16 pages of 16 bytes of EEPROM each. The 48-bit EUI address in the AT24MAC402 are located in the extended memory block. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
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