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2020-02-05dm: core: Create a new header file for 'compat' featuresSimon Glass1-0/+1
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07arm: socfpga: Convert system manager from struct to definesLey Foon Tan2-8/+3
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-12-02common: Move ARM cache operations out of common.hSimon Glass2-0/+2
These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02common: Move some cache and MMU functions out of common.hSimon Glass1-0/+1
These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-10-24arm64: zynqmp: Convert invoke_smc() to xilinx_pm_request()Michal Simek1-7/+9
Remove macros which use PM_SIP_SVC offset and convert invoke_smc() to xilinx_pm_request() which do calculation with PM_SIP_SVC already. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24arm64: versal: Rename versal_pm_request to xilinx_pm_requestMichal Simek1-1/+1
Use generic name instead of Versal specific because this should be also used on ZynqMP. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24arm64: xilinx: Move firmware functions from platform to driverMichal Simek1-0/+1
versal_pm_request() and invoke_smc() are almost the same. Only one difference is that versal_pm_request is adding PM_SIP_SVC offset to api_id. The patch is moving platform implementation to firmware driver code for synchronization. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
2019-10-08arm64: zynqmp: use firmware driver to get versionIbai Erkiaga1-2/+2
Use the new function from firmware version to get the firmware version. Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08firmware: zynqmp: create firmware headerIbai Erkiaga1-0/+1
New firmware header to place firmware specific macro and function declarations. The patch also moves the macros defining PM operations as well as some helper macros. Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08fpga: zynqmp: Fix second local variable declarationMichal Simek1-1/+1
No reason to define new_buf again. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08arm64: versal: fpga: Add PL bit stream load supportSiva Durga Prasad Paladugu4-1/+68
This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30fpga: altera: cyclon2: Check function pointer before callingAlexander Dahl1-1/+5
As already done for the 'pre' function, a check is added to not follow a NULL pointer, if somebody has not assigned a 'post' function. Signed-off-by: Alexander Dahl <ada@thorsis.com>
2019-07-30fpga: altera: cyclon2: Fix indentationAlexander Dahl1-16/+16
Some code parts stood too far left … Signed-off-by: Alexander Dahl <ada@thorsis.com>
2019-07-30fpga: altera: cyclon2: Fix most checkpatch warningsAlexander Dahl1-42/+39
Nothing special, but done before further cleanup. * spacing * braces * __FUNCTION__ → __func__ Suggested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Alexander Dahl <ada@thorsis.com>
2019-07-30fpga: virtex2: Add slave serial programming supportRobert Hancock1-13/+83
This adds support for slave serial programming, in addition to the previously supported slave SelectMAP mode. There are two ways that this can be used: -Using the clk and wdata callbacks in order to write image data one bit at a time using pure bit-banging. This works, but is rather painfully slow with typical image sizes. -By specifying the wbulkdata callback instead, the image loading process can be offloaded to SPI hardware. In this mode the clk and wdata callbacks do not need to be specified. This allows the image to be loaded much faster, taking only a few seconds with even relatively large images. Slave serial programming has been tested on the Kintex-7 series of FPGAs. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30fpga: virtex2: Add additional clock cycles after DONE assertionRobert Hancock1-4/+16
Some Xilinx FPGA configuration options can result in the startup sequence extending past the end of the FPGA bitstream. Continue applying CCLK clock cycles for 8 cycles after DONE is asserted in order to ensure the startup sequence is complete, as recommended by Xilinx. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30fpga: virtex2: Split out image writing from pre/post operationsRobert Hancock1-157/+174
This is in preparation for adding slave serial programming support, which uses the same pre/post operations as slave SelectMAP, to avoid duplicating code. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30fpga: virtex2: added Kconfig optionRobert Hancock1-0/+8
Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30fpga: virtex2: cosmetic: Cleanup code styleRobert Hancock1-134/+136
Address Checkpatch warnings in virtex2 code prior to making other changes. No functional change intended. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-21fpga: arria10: Fix error in fpga pin configurationDalon Westergreen1-4/+5
Pin configuration of the FPGA devicetree block should be done after core configuration in the arria10 fpga driver. This fix corrects the check of status, and ensures that the fpga pin mux is configured on correct configuration of the core fpga image. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
2019-05-10spl: socfpga: Implement fpga bitstream loading with socfpga loadfsTien Fong Chee1-1/+1
Add support for loading FPGA bitstream to get DDR up running before U-Boot is loaded into DDR. Boot device initialization, generic firmware loader and SPL FAT support are required for this whole mechanism to work. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-10ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loadingTien Fong Chee1-13/+484
Add FPGA driver to support program FPGA with FPGA bitstream loading from filesystem. The driver are designed based on generic firmware loader framework. The driver can handle FPGA program operation from loading FPGA bitstream in flash to memory and then to program FPGA. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-10ARM: socfpga: Moving the watchdog reset to the for-loop status pollingTien Fong Chee1-1/+1
Current watchdog reset is misplaced after for-loop status polling, so this poses a risk that watchdog can't be reset timely if polling taking longer than watchdog timeout. This patch moving the watchdog reset into polling to ensure the watchdog can be reset timely. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-10ARM: socfpga: Cleaning up and ensuring consistent format messages in driverTien Fong Chee1-6/+7
Ensure all the debug messages are always prefix with "FPGA: " and comment beginning with uppercase letter. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-04-16arm: zynq: Add an info message about post configSiva Durga Prasad Paladugu1-0/+2
Post configuration cant be run at u-boot as u-boot didn't has any info about the design.So,this patch adds an info message that post config was not run and needs to be run manually if needed. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16fpga: Replace char * with const char * for filenameTien Fong Chee1-1/+2
Ensure the string for filename is always constant, otherwise it can be corrupted by the writing. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-18ARM: socfpga: stratix10: Return valid error code from FPGA driverAng, Chee Hong1-11/+6
This patch prevent the Stratix 10 FPGA driver incorrectly return the transaction ID as the mailbox error code. It should always return the actual mailbox error code from SDM firmware. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2019-01-24fpga: zynqmp: show an error message when FPGA programming failsLuca Ceresoli1-1/+1
When FPGA programming fails, it does so silently, unless debugging code is enabled. This makes it hard to detect problems in production environments. Print the error message unconditionally so the error doesn't go unnoticed. Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-12-20arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device tableAng, Chee Hong1-0/+6
Enable 'fpga' command in u-boot. User will be able to use the FPGA command to program the FPGA on Stratix10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2018-12-20arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration DriverAng, Chee Hong3-0/+300
Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2018-10-31arm: socfpga: fpga: fix type of local variableSimon Goldschmidt2-2/+2
The 'status' variable in 'socfpga_load()' for both gen5 and arria10 is of type 'unsigned long' while it is always used as 'int' only. Change it to 'int'. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-09-26fpga: zynqmp: Modify PL bitstream loading sequenceSiva Durga Prasad Paladugu1-10/+25
This patch modifies PL bitstream loading sequence as per latest Xilfpga which supports all variants of bitstream images generated from vivado and from bootgen. With this new change in Xilfpga, uboot doesn't need to validate and swap bitstream as it will be taken care inside Xilfpga. ZynqMP PL driver now checks for supporting PMUFW version before skipping the validation and swap sequence as there can be old PMUFW which doesn't supports this feature. In this case, driver uses old way of PL bitstream loading sequence. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-09-11fpga: Kconfig: Replace spaces with tabsMichal Simek1-8/+8
Trivial Kconfig cleanup. Use tabs instead of spaces. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19drivers: fpga: zynqpl: fix compilation with SPLLuis Araneda1-2/+2
Disable the use of function zynq_loadfs when compiling the driver for the SPL, as the following filesystem functions are not found by the linker: - fs_set_blk_dev - fs_read - fs_set_blk_dev - fs_read - fs_read Signed-off-by: Luis Araneda <luaraneda@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19xilinx: zynq: Add support to secure imagesSiva Durga Prasad Paladugu1-0/+45
This patch basically adds two new commands for loadig secure images. 1. zynq rsa adds support to load secure image which can be both authenticated or encrypted or both authenticated and encrypted image in xilinx bootimage(BOOT.bin) format. 2. zynq aes command adds support to decrypt and load encrypted image back to DDR as per destination address. The image has to be encrypted using xilinx bootgen tool and to get only the encrypted image from tool use -split option while invoking bootgen. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-01fpga: zynqmp: Add secure bitstream loading for ZynqMPSiva Durga Prasad Paladugu2-0/+66
This patch adds support for loading secure bitstreams on ZynqMP platforms. The secure bitstream images has to be generated using Xilinx bootgen tool. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-01cmd: fpga: Add support to load secure bitstreamsSiva Durga Prasad Paladugu1-0/+29
This patch adds support to load secure bitstreams(authenticated or encrypted or both). As of now, this feature is added and tested only for xilinx bitstreams and the secure bitstream was generated using xilinx bootgen tool, but the command is defined in more generic way. Command example to load authenticated and device key encrypted bitstream is as follows "fpga loads 0 100000 2000000 0 1" Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini18-36/+18
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTRTom Rini3-6/+0
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27arm: socfpga: Fix with the correct polling on bit is setTien Fong Chee1-5/+5
Commit 2baa997240d ("arm: socfpga: Add FPGA driver support for Arria 10") Polling on wrong cleared bit. Fix with correct polling on bit is set. Fixes: 2baa997240d ("arm: socfpga: Add FPGA driver support for Arria 10") Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-04-09fpga: zynq: Add delay after PCFG_PROG_B changeSiva Durga Prasad Paladugu1-0/+16
There is delay needed after PCFG_PROGB change if AES key source is efuse. This fixes the issue of encrypted bitstream loading with AES efuse as key source. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-09fpga: zynqmp: Fix the nonsecure bitstream loading issueSiva Durga Prasad Paladugu1-2/+6
Xilfpga library expects the size of bitstream in a pointer but currenly we are passing the size as a value. This patch fixes this issue. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-09fpga: zynqmp: Update zynqmp_load() as per latest xilfpgaSiva Durga Prasad Paladugu1-5/+1
Latest xilfpga expects to set BIT5 of flags for nonsecure bitsream and also expects length in bytes instead of words This patch does the same. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-09fpga: zynqmp: Add support to get the PCAP status for fpga info commandNitin Jain1-0/+14
This patch adds support for ZynqMP platform to print FPGA PCAP status for "fpga status" command. Signed-off-by: Nitin Jain <nitinj@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23fpga: Simplify error path in fpga_addMichal Simek1-10/+11
Check !desc earlier to simplify code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Reviewed-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
2018-02-28arm: zynq: fpga: Added Kconfig support for CONFIG_FPGA_ZYNQPLVipul Kumar1-0/+7
This patch added Kconfig support for CONFIG_FPGA_ZYNQPL and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2018-02-28fpga: Added Kconfig support for FPGA_SPARTAN3Vipul Kumar1-0/+5
This patch added Kconfig support for FPGA_SPARTAN3 and migrates the values over to the defconfigs. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2018-01-24wait_bit: use wait_for_bit_le32 and remove wait_for_bitÁlvaro Fernández Rojas1-10/+7
wait_for_bit callers use the 32 bit LE version Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-12-14fpga: allow programming fpga from FIT image for all FPGA driversGoldschmidt Simon2-0/+22
This drops the limit that fpga is only loaded from FIT images for Xilinx. This is done by moving the 'partial' check from 'common/image.c' to 'drivers/fpga/xilinx.c' (the only driver supporting partial images yet) and supplies a weak default implementation in 'drivers/fpga/fpga.c'. Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Tested-by: Michal Simek <michal.simek@xilinx.com> (On zcu102) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-26arm: socfpga: Enhance FPGA program write rbf data with size >= 4 bytesTien Fong Chee1-6/+8
Existing FPGA program write is always assume RBF data >= 32 bytes, so any rbf data less than 32 bytes writing to FPGA would be failed. This patch enhances the FPGA program write to support rbf data with size >= 4 bytes. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
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