aboutsummaryrefslogtreecommitdiff
path: root/drivers/ddr
AgeCommit message (Expand)AuthorFilesLines
2017-07-12driver/ddr: Add support for setting timing in hws_topology_mapMarek Behún2-0/+15
2017-06-16treewide: remove unneeded semicolonsMasahiro Yamada1-1/+1
2017-06-12driver: ddr: fsl: Fix compiling error for DDR2York Sun1-0/+4
2017-06-05common: arm: freescale: layerscape: Move header files out of common.hSimon Glass4-4/+8
2017-06-05common: freescale: Move arch-specific declarationsSimon Glass5-0/+13
2017-04-18Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini1-36/+36
2017-04-18ddr: fsl: incorrect logical constraint in populate_memctl_optionsxypron.glpk@gmx.de1-1/+1
2017-04-17drivers: ddr: fsl: fix unused-const-variable warningsThomas Schaefer1-36/+36
2017-04-14Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini3-1/+9
2017-04-14arm: socfpga: Convert Altera DDR SDRAM driver to use KconfigLey Foon Tan3-1/+9
2017-04-13board_f: Rename initdram() to dram_init()Simon Glass1-2/+2
2017-04-05board_f: Drop return value from initdram()Simon Glass1-0/+2
2017-01-04ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLSYork Sun9-64/+64
2017-01-04ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to KconfigYork Sun1-0/+14
2017-01-04powerpc: mpc85xx: Move CONFIG_SYS_FSL_ERRATUM_* to KconfigYork Sun1-0/+15
2017-01-04arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to KconfigYork Sun1-0/+21
2017-01-04fsl_ddr: Move DDR config options to driver KconfigYork Sun2-1/+123
2016-12-05fsl/ddr: Add erratum_a009942_check_cpo and clean related erratumShengzhou Liu3-31/+134
2016-12-05fsl/ddr: Fix compiling warningShengzhou Liu1-32/+25
2016-11-23powerpc: MPC8555: Remove macro CONFIG_MPC8555York Sun2-2/+2
2016-11-23powerpc: mpc8541: Remove macro CONFIG_MPC8541York Sun2-2/+2
2016-10-27ddr: altera: Configuring SDRAM extra cycles timing parametersChin Liang See1-0/+3
2016-10-06Various, accumulated typos collected from around the tree.Robert P. J. Day1-1/+1
2016-09-26Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini4-40/+213
2016-09-26driver: ddr: fsl_mmdc: Pass board parameters through data structureYork Sun1-19/+19
2016-09-23drivers: squash lines for immediate returnMasahiro Yamada3-25/+5
2016-09-14ddr: fsl: fix a compile issueShaohui Xie1-1/+6
2016-09-14driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012aShengzhou Liu2-0/+157
2016-09-14driver/ddr/fsl: Revise workaround A008511 for A009803York Sun1-36/+47
2016-09-14driver/ddr/fsl: Add more debug registersYork Sun2-3/+3
2016-08-02driver/ddr/fsl: Fix timing_cfg_2York Sun1-1/+1
2016-07-16Various, unrelated tree-wide typo fixes.Robert P. J. Day1-1/+1
2016-06-03driver/ddr/fsl: Check condition for erratum A-009803Shengzhou Liu1-19/+23
2016-06-03drivers/ddr/fsl: Disabling data init if ECC is not enabledYork Sun1-1/+2
2016-06-03drivers/ddr/fsl: Fix timing_cfg_2 registerYork Sun1-1/+1
2016-06-03drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntlShengzhou Liu1-2/+9
2016-05-24Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini1-4/+23
2016-05-20arm: mvebu: a38x: Weed out floating point useMarek Vasut1-19/+10
2016-05-18driver/ddr/fsl: Add workaround for erratum A-010165Shengzhou Liu1-1/+9
2016-05-17driver/ddr/fsl: Add workaround for erratum A-009801Shengzhou Liu1-0/+7
2016-05-17drivers/ddr/fsl: update workaround for erratum A-008511Shengzhou Liu1-3/+7
2016-05-02Fix spelling of "occurred".Vagrant Cascadian2-2/+2
2016-04-20ddr: altera: Repair DQ window centering codeMarek Vasut1-8/+7
2016-04-20ddr: altera: Staticize global variablesMarek Vasut1-4/+4
2016-04-20ddr: altera: Make DLEVEL behavior inclusiveMarek Vasut1-66/+66
2016-04-20ddr: altera: Zero DM IN delay in scc_mgr_zero_group()Marek Vasut1-3/+13
2016-04-20ddr: altera: Remove unnecessary ODT mode configMarek Vasut1-1/+0
2016-04-20ddr: altera: Remove unnecessary update of the SCCMarek Vasut1-1/+0
2016-04-20ddr: altera: Fix DRAM end value in protection ruleMarek Vasut1-1/+1
2016-04-20ddr: altera: Fix scc_mgr_set() argument orderMarek Vasut1-1/+1
generated by cgit v1.1 at 2024-07-13 19:55:26 +0000