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2022-06-22crypto: nuvoton: Add NPCM7xx SHA driverJim Liu3-0/+904
add nuvoton BMC npcm750 SHA driver Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-22crypto: nuvoton: Add NPCM7xx AES driverJim Liu5-0/+313
add nuvoton BMC npcm750 AES driver Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-16crypto: fsl_hash: Remove unnecessary alignment check in caam_hash()Stefan Roese1-6/+0
While working on an LX2160 based board and updating to latest mainline I noticed problems using the HW accelerated hash functions on this platform, when trying to boot a FIT Kernel image. Here the resulting error message: Using 'conf-freescale_lx2160a.dtb' configuration Trying 'kernel-1' kernel subimage Verifying Hash Integrity ... sha256Error: Address arguments are not aligned CAAM was not setup properly or it is faulty error! Bad hash value for 'hash-1' hash node in 'kernel-1' image node Bad Data Hash ERROR: can't get kernel image! Testing and checking with Gaurav Jain from NXP has revealed, that this alignment check is not necessary here at all. So let's remove this check completely. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Gaurav Jain <gaurav.jain@nxp.com> Cc: dullfire@yahoo.com Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
2022-05-20crypto/fsl: fsl_hash: Fix dcache issue in caam_hash_finishGaurav Jain1-0/+8
HW accelerated hash operations are giving incorrect hash output. so add flush and invalidate for input/output hash buffers. Fixes: 94e3c8c4fd (crypto/fsl - Add progressive hashing support using hardware acceleration.) Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
2022-05-19i.MX8 crypto/fsl: Enable fsl CAAM rng driverGaurav Jain1-1/+7
rng driver enabled to read random number using caam. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
2022-05-19i.MX6SX: crypto/fsl: fix entropy delay valueGaurav Jain1-1/+10
RNG Hardware error is reported due to incorrect entropy delay rng self test are run to determine the correct ent_dly. test is executed with different voltage and temperature to identify the worst case value for ent_dly. after adding a margin value(1000), ent_dly should be at least 12000. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-04-21crypto/fsl: add invalidate_dcache_range for hash output bufferGaurav Jain1-6/+8
HW accelerated hash operations are giving incorrect hash output. so invalidate cache lines to avoid cache overwriting in DDR memory region. caam_hash() -moved address alignment check in the beginning of function. -added invalidate_dcache_range for pout buffer before running descriptor. Fixes: d7af2baa49 (crypto/fsl: Fix HW accelerated hash commands) Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-04-21crypto/fsl: Clear the memory when blob decapsulation failsGaurav Jain1-0/+4
issue: blob decapsulation operation store the decrypted data in memory even if ICV check failed. fix: clear the blob data output memory. Fixes: c5de15cbc8 (crypto/fsl: Add command for encapsulating/decapsulating blobs) Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Kshitiz Varshney <kshitiz.varshney@nxp.com> Tested-by: Kshitiz Varshney <kshitiz.varshney@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-04-12crypto/fsl: i.MX8: Enable Job ring driver model.Gaurav Jain2-3/+46
i.MX8(QM/QXP) - added support for JR driver model. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-04-12crypto/fsl: Add support for CAAM Job ring driver modelGaurav Jain3-114/+241
added device tree support for job ring driver. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-02-21crypto: aspeed: fix polling RSA status wrong issueNeal Liu1-1/+1
Check interrupt status to see if RSA engine is completed. After completion of the task, write-clear the status to finish operation. Add missing register base for completion. Fixes: 89c36cca0b6 ("crypto: aspeed: Add AST2600 ACRY support") Signed-off-by: Neal Liu <neal_liu@aspeedtech.com> Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2022-01-19doc: replace @return by Return:Heinrich Schuchardt3-6/+6
Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-11-17crypto: aspeed: Add AST2600 ACRY supportChia-Wei Wang3-0/+201
ACRY is designed to accelerate ECC/RSA digital signature generation and verification. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17crypto: aspeed: Add AST2600 HACE supportJohnny Huang6-0/+403
Hash and Crypto Engine (HACE) is designed to accelerate the throughput of hash data digest, and symmetric-key encryption. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-11-09board: fsl_validate: Fix Double free IssueKshitiz Varshney1-7/+7
Remove Double free issue from calc_img_key_hash() and calc_esbchdr_esbc_hash() function. Verified the secure boot changes using lx2162aqds board. Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-09-30WS cleanup: remove SPACE(s) followed by TABWolfgang Denk1-1/+1
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-16Merge tag 'v2021.10-rc4' into nextTom Rini1-0/+2
Prepare v2021.10-rc4 Signed-off-by: Tom Rini <trini@konsulko.com> # gpg: Signature made Tue 14 Sep 2021 06:58:32 PM EDT # gpg: using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C # gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate] # Conflicts: # board/Arcturus/ucp1020/spl.c # cmd/mvebu/Kconfig # common/Kconfig.boot # common/image-fit.c # configs/UCP1020_defconfig # configs/sifive_unmatched_defconfig # drivers/pci/Kconfig # include/configs/UCP1020.h # include/configs/sifive-unmatched.h # lib/Makefile # scripts/config_whitelist.txt
2021-09-08image: Drop if/elseif hash selection in calculate_hash()Alexandru Gagniuc1-0/+2
calculate_hash() would try to select the appropriate hashing function by a if/elseif contruct. But that is exactly why hash_lookup_algo() exists, so use it instead. This does mean that we now have to 'select HASH' to make sure we get the hash_lookup_algo() symbol. However, the change makes sense because even basic FITs will have to deal with "hash" nodes. My only concern is that the 'select SPL_HASH' might cause some platform to grow above its SPL size allowance Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> [trini: Make FSL_CAAM be implied only on ARM && SPL] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-01crypto: hash: Add software hash DM driverChia-Wei Wang3-0/+313
Add purely software-implmented drivers to support multiple hash operations including CRC, MD5, and SHA family. This driver is based on the new hash uclass. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-09-01dm: hash: Add new UCLASS_HASH supportChia-Wei Wang5-0/+134
Add UCLASS_HASH for hash driver development. Thus the hash drivers (SW or HW-accelerated) can be developed in the DM-based fashion. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-08-18crypto/fsl: fix missed dma_addr_t -> caam_dma_addr_t conversionHoria Geantă1-1/+1
One of the "dma_addr_t" instances was left out when converting to "caam_dma_addr_t". Fixes: 2ff17d2f74c5 ("crypto: fsl: refactor for 32 bit version CAAM support on ARM64") Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-07-06dm: define LOG_CATEGORY for all uclassPatrick Delaunay1-0/+2
Define LOG_CATEGORY for all uclass to allow filtering with log command. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-08crypto: fsl: refactor for 32 bit version CAAM support on ARM64Ye Li8-72/+93
Previous patch "MLK-18044-4: crypto: caam: Fix pointer size to 32bit for i.MX8M" breaks the 64 bits CAAM. Since i.MX CAAM are all 32 bits no matter the ARM arch (32 or 64), to adapt and not break 64 bits CAAM support, add a new config CONFIG_CAAM_64BIT and new relevant type "caam_dma_addr_t". This config is default enabled when CONFIG_PHYS_64BIT is set except for iMX8M. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08fsl_mfgprot: Fix typo in sign_mppubk()Breno Lima1-1/+1
The signature is generated using manufacturing protection private key. Fix typo in fsl_mfgprot.c. Signed-off-by: Breno Lima <breno.lima@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08imx8m: Add DEK blob encapsulation for imx8mClement Faure1-2/+1
Add DEK blob encapsulation support for IMX8M through "dek_blob" command. On ARMv8, u-boot runs in non-secure, thus cannot encapsulate a DEK blob for encrypted boot. The DEK blob is encapsulated by OP-TEE through a trusted application call. U-boot sends and receives the DEK and the DEK blob binaries through OP-TEE dynamic shared memory. To enable the DEK blob encapsulation, add to the defconfig: CONFIG_SECURE_BOOT=y CONFIG_FAT_WRITE=y CONFIG_CMD_DEKBLOB=y Signed-off-by: Clement Faure <clement.faure@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08crypto: caam: Fix pointer size to 32bit for i.MX8MAymen Sghaier5-32/+36
The CAAM block used in i.MX8M is 32 bits address size but when the flag PHYS_64BIT is enabled for armv8, the CAAM driver will try to use a wrong pointer size. This patch fixes this issue. Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08crypto: caam: Fix build warnings pointer castingAymen Sghaier1-2/+3
Enabling CAAM driver for i.MX8M platforms, a 64 bits architecture, lead to casting warnings: from/to pointer to/from integer with different size. This patch fix these warnings Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08crypto: caam: Add CAAM support to i.MX8M platformsAymen Sghaier1-1/+3
This patch enable CAAM support for i.MX8M platforms. Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08caam: enable support for iMX7ULPFranck LENORMAND1-1/+1
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08crypto: caam: change JR running loopFranck LENORMAND2-7/+9
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08crypto: fsl: blob: Flush dcache range for destination addressBreno Lima1-0/+6
The blob command is not working on i.MX7D, i.MX8MQ and i.MX8MM devices. Due to different cache management it's necessary to flush dcache range for destination address so data can be available in memory. Add necessary operations in blob_encap() and blob_decap() functions. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08imx: imx7 Support for Manufacturing ProtectionBreno Lima3-0/+162
This code was originally developed by Raul Cardenas <raul.casas@nxp.com> and modified to be applied in U-Boot imx_v2017.03. More information about the initial submission can be seen in the link below: https://lists.denx.de/pipermail/u-boot/2016-February/245273.html i.MX7D has an a protection feature for Manufacturing process. This feature uses asymmetric encryption to sign and verify authenticated software handled between parties. This command enables the use of such feature. The private key is unique and generated once per device. And it is stored in secure memory and only accessible by CAAM. Therefore, the public key generation and signature functions are the only functions available for the user. The manufacturing-protection authentication process can be used to authenticate the chip to the OEM's server. Command usage: Print the public key for the device. - mfgprot pubk Generates Signature over given data. - mfgprot sign <data_address> <data_size> Signed-off-by: Raul Ulises Cardenas <raul.casas@nxp.com> Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-02-02common: Drop asm/global_data.h from common headerSimon Glass1-0/+1
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-05dm: Rename U_BOOT_DEVICE() to U_BOOT_DRVINFO()Simon Glass2-2/+2
The current macro is a misnomer since it does not declare a device directly. Instead, it declares driver_info record which U-Boot uses at runtime to create a device. The distinction seems somewhat minor most of the time, but is becomes quite confusing when we actually want to declare a device, with of-platdata. We are left trying to distinguish between a device which isn't actually device, and a device that is (perhaps an 'instance'?) It seems better to rename this macro to describe what it actually is. The macros is not widely used, since boards should use devicetree to declare devices. Rename it to U_BOOT_DRVINFO(), which indicates clearly that this is declaring a new driver_info record, not a device. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass1-1/+1
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-27crypto/fsl: add RNG supportMichael Walle6-0/+125
Register the random number generator with the rng subsystem in u-boot. This way it can be used by EFI as well as for the 'rng' command. Signed-off-by: Michael Walle <michael@walle.cc> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27crypto/fsl: instantiate the RNG with prediciton resistanceMichael Walle4-7/+76
If it is already instantiated tear it down first and then reinstanciate it again with prediction resistance. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27crypto/fsl: don't regenerate secure keysMichael Walle3-7/+8
The secure keys (TDKEK, JDKEK, TDSK) can only be generated once after a POR. Otherwise the RNG4 will throw an error. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27crypto/fsl: support newer SEC modulesMichael Walle1-2/+10
Since Era 10, the version registers changed. Add the version registers and use them on newer modules. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27crypto/fsl: export caam_get_era()Michael Walle1-1/+9
We need the era in other modules, too. For example, to get the RNG version. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27crypto/fsl: make SEC%u status line consistentMichael Walle1-7/+7
Align the status line with all the other output in U-Boot. Before the change: DDR 3.9 GiB (DDR3, 32-bit, CL=11, ECC on) SEC0: RNG instantiated WDT: Started with servicing (60s timeout) After the change: DDR 3.9 GiB (DDR3, 32-bit, CL=11, ECC on) SEC0: RNG instantiated WDT: Started with servicing (60s timeout) Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27crypto/fsl: unused value in caam_hash_update()Heinrich Schuchardt1-1/+1
The value 0 assigned to final is overwritten before ever being used. Remove the assignment. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27crypto/fsl: correct printf() statement.Heinrich Schuchardt1-2/+2
The sequence of arguments should match the format string. For printing unsigned numbers we should use %u. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27crypto/fsl: fix unaligned accessMichael Walle1-14/+13
On aarch64 running with dcache off, will result in an unaligned access exception: => dcache off => hash sha1 $kernel_addr_r 100 "Synchronous Abort" handler, esr 0x96000061 elr: 00000000960317d8 lr : 00000000960316a4 (reloc) elr: 00000000fbd787d8 lr : 00000000fbd786a4 [..] The compiler emits a "stur x1, [x0, #12]". x1 is might just be 32 bit aligned pointer. Remove the unused u64 element from the union to drop the minimal alignment to 32 bit. Also remove the union, because it is no more needed. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-19drivers: crypto: mod_exp_sw: Re-add DM_FLAG_PRE_RELOCJan Kiszka1-0/+1
This driver is safe to use in SPL without relocation. Denying DM_FLAG_PRE_RELOC prevents its usability for verifying the main U-Boot or other artifacts from the SPL unless needless enabling the full driver set (SPL_OF_PLATDATA). Fixes: 17e117408571 ("drivers: crypto: rsa_mod_exp: avoid DM_FLAG_PRE_RELOC") CC: Heinrich Schuchardt <xypron.glpk@gmx.de> CC: Marek Vasut <marex@denx.de> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2020-05-18common: Drop log.h from common headerSimon Glass7-0/+7
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop net.h from common headerSimon Glass5-0/+6
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-16drivers: crypto: rsa_mod_exp: avoid DM_FLAG_PRE_RELOCHeinrich Schuchardt2-2/+0
Function rsa_verify_key() is not called before relocation. So there is no need to load the UCLASS_MOD_EXP drivers before relocation. This avoid a failure to boot for pine64-lts_defconfig with CONFIG_RSA=y. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-01-25crypto: make mod_exp_sw() staticHeinrich Schuchardt1-2/+2
Function mod_exp_sw() is only used via the operators of the uclass. It is not defined in any include. Make mod_exp_sw() static. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-12-02common: Move ARM cache operations out of common.hSimon Glass4-0/+4
These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-08-14 07:25:57 +0000