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2016-04-24clk: uniphier: add Media I/O clock driver support for PH1-LD20Masahiro Yamada1-0/+4
PH1-LD20 needs this for its SD card controller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-01clk: uniphier: use devm_get_addr() to get base addressMasahiro Yamada1-6/+3
Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14clk: uniphier: add Media I/O clock driver for UniPhier SoCsMasahiro Yamada7-0/+413
This is the initial commit for the UniPhier clock drivers. Currently, only the Media I/O clock is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-01drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.Purna Chandra Mandal2-0/+434
PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers and dividers capable of supplying clock to various controllers on or off-chip. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-21rockchip: spl: Support full-speed CPU in SPLSimon Glass1-0/+56
Add a feature which speeds up the CPU to full speed in SPL to minimise boot time. This is only supported for certain boards (at present only jerry). Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21rockchip: rk3288: clock: Fix various minor errorsSimon Glass1-8/+13
Fix a number of small errors which were found in reviewing the clock code. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21rockchip: clk: Add support for clocks needed by the displaysSimon Glass1-4/+170
The displays need to use NPLL and also select some new peripheral clocks. Add support for these to the clock driver. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21rockchip: Rename the CRU_MODE_CON fieldsSimon Glass1-30/+9
These should match the datasheet naming. Adjust them. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21rockchip: clk: Make rkclk_get_clk() SoC-specificSimon Glass2-0/+30
The current method assumes that clocks are numbered from 0 and we can determine a clock by its number. It is safer to use an ID in the clock's platform data to avoid the situation where another clock is bound before the one we expect. Move the existing code into rk3036 since it still works there. Add a new implementation for rk3288. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21dm: clk: Add a simple version of clk_get_by_index()Simon Glass1-1/+17
This function adds quite a bit of code to SPL and we probably don't need all the features in SPL. Add a simple version (for SPL only) to save space. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21rockchip: mmc: Update the driver to use the new clock IDSimon Glass1-1/+1
We can use the new clk_get_by_index() function to get the correct clock. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21rockchip: clock: Add a function to find a clock by IDSimon Glass1-2/+22
The current approach of using uclass_get_device() is error-prone. Another clock (for example a fixed-clock) may cause it to break. Add a function that does a proper search. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21rockchip: clk: Add a function to get a peripheral clock rateSimon Glass1-0/+37
It is useful to be able to read the rate of a peripheral clock. Add a handler for that. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21rockchip: clock: Rename the general clock variable to gclk_rateSimon Glass1-12/+12
The current name is confusing and a bit verbose. Rename it. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21rockchip: Use a separate clock ID for clocksSimon Glass2-36/+43
At present we use the same peripheral ID for clocks and pinctrl. While this works it is probably better to use the device tree clock binding ID for clocks. We can use the clk_get_by_index() function to find this. Update the clock drivers and the code that uses them. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21dm: clk: Add support for decoding clocks from the device treeSimon Glass1-0/+28
Add a method which can locate a clock for a device, given its index. This uses the normal device tree bindings to return the clock device and the first argument which is normally used as a peripheral ID in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-21clk: add fixed rate clock driverMasahiro Yamada2-1/+58
This commit intends to implement "fixed-clock" as in Linux. (drivers/clk/clk-fixed-rate.c in Linux) If you need a very simple clock to just provide fixed clock rate like a crystal oscillator, you do not have to write a new driver. This driver can support it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20clk: add API to enable clockMasahiro Yamada1-0/+10
The most basic thing for clock is to enable it, but it is missing in this uclass. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20clk: add static qualifier to local functionsMasahiro Yamada3-4/+5
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20clk: move Kconfig options into sub-menuMasahiro Yamada1-0/+4
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01rockchip: rk3036: Add clock driverhuang lin2-0/+415
Add a driver for setting up and modifying the various PLLs, peripheral clocks and mmc clocks on RK3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-09-02rockchip: rk3288: Add clock driverSimon Glass2-0/+619
Add a driver for setting up and modifying the various PLLs and peripheral clocks on the RK3288. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-18clk: rename CONFIG_SPL_CLK_SUPPORT to CONFIG_SPL_CLKMasahiro Yamada1-1/+1
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-07-21dm: test: Add tests for the clk uclassSimon Glass2-0/+86
Add tests of each API call using a sandbox clock device. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-07-21dm: Add a clock uclassSimon Glass3-0/+85
Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
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