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2020-02-28versal: drivers: clk: Fix invalid clock name queriesRajan Vaja1-0/+6
The clock driver makes EEMI call to get the name of invalid clk when executing versal_get_clock_info() function. This results in error messages. Added check for validating clock before saving clock attribute and calling versal_pm_clock_get_name() in versal_get_clock_info() function. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-02-14Merge tag 'u-boot-stm32-20200214' of ↵Tom Rini1-4/+5
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - add DH Electronics DHCOM SoM and PDK2 board - DT alignment with kernel v5.5-rc7 for stm32mp1 boards - fix STM32 image format for big endian hosts in mkimage - solve warnings in device tree and code for stm32mp1 boards - remove fdt_high and initrd_high for stm32 and stih boards - add support of STM32MP15x Rev.Z - update stm32mp1 readme
2020-02-13clk: stm32mp1: solve type issue in stm32mp1_lse_enable and stm32mp1_clktreePatrick Delaunay1-4/+5
Solve type issue in stm32mp1_lse_enable and stm32mp1_clktree. This patch solves the warnings when compiling with W=1 on stm32mp1 board: clk_stm32mp1.c: In function ‘stm32mp1_lse_enable’: clk_stm32mp1.c:1238:15: warning: comparison of integer expressions of different signedness: ‘u32’ {aka ‘unsigned int’} and ‘int’ [-Wsign-compare] clk_stm32mp1.c:1239:13: warning: comparison of integer expressions of different signedness: ‘u32’ {aka ‘unsigned int’} and ‘int’ [-Wsign-compare] clk_stm32mp1.c: In function ‘stm32mp1_clktree’: clk_stm32mp1.c:1814:17: warning: comparison of integer expressions of different signedness: ‘int’ and ‘unsigned int’ [-Wsign-compare] Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-02-12CLK: HSDK: fix HDMI clock calculationEugeniy Paltsev1-10/+21
HDMI PLL has its own xtal with 27 MHz output but we treat it the same way as other PLLs with 33.33 MHz input. Fix that. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-02-12CLK: HSDK: Check for PLL bypass firstlyEugeniy Paltsev1-4/+4
Pll bypass has priority over enable/disable. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-02-11Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dmTom Rini47-6/+79
sandbox conversion to SDL2 TPM TEE driver Various minor sandbox video enhancements New driver model core utility functions
2020-02-07x86: Add a clock driver for Intel devicesSimon Glass4-0/+58
So far we have avoided adding a clock driver for Intel devices. But the Designware I2C driver needs a different clock (133MHz) on Intel devices than on others (166MHz). Add a simple driver that provides this information. This driver can be expanded later as needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-05dm: core: Create a new header file for 'compat' featuresSimon Glass30-0/+34
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: core: Require users of devres to include the headerSimon Glass27-1/+40
At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-02-05clk: Rename free() to rfree()Simon Glass4-5/+5
This function name conflicts with our desire to #define free() to something else on sandbox. Since it deals with resources, rename it to rfree(). Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-30arm: rockchip: Add common cru.hJagan Teki2-39/+39
Few of the rockchip family SoC atleast rk3288, rk3399 are sharing some cru register bits so adding common code between these SoC families would require to include both cru include files that indeed resulting function declarations error. So, create a common cru include as cru.h then include the rk3399 arch cru include file and move the common cru register bit definitions into it. The rest of rockchip cru files will add it in future. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-26clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate()Giulio Benetti1-2/+8
Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-26clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate()Giulio Benetti1-0/+3
Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-26clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate()Giulio Benetti1-2/+8
Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-26clk: Fix error checking of dev_read_addr_ptrSean Anderson3-3/+3
dev_read_addr_ptr returns NULL on error, not FDT_ADDR_T_NONE. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-01-26clk: uclass: clk_get_by_name() must not be available if CONFIG_OF_PLATDATA ↵Giulio Benetti1-1/+1
is enabled clk_get_by_name() requires clk_get_by_id() that is not available if CONFIG_OF_PLATDATA is defined, so move clk_get_by_name() into #else condition of #if CONFIG_IS_ENABLED(OF_PLATDATA). Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-26clk: show more error info when uclass_get_device_by_namePeng Fan1-2/+4
It will ease debug when uclass_get_device_by_name failed with more error info printed out. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-26clk: mediatek: use unsigned type for returning the clk rateFabien Parent1-1/+1
mtk_clk_find_parent_rate is calling clk_get_rate to know the rate of a parent clock. clk_get_rate returns a ulong, while mtk_clk_find_parent_rate returns an int. This implicit cast creates an issue for clock rates big enough to need the full 32 bits to store its data. When that happen the clk rate will become incorrect because of the implicit cast between ulong -> int -> ulong. This commit change the return type of mtk_clk_find_parent_rate to ulong. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2020-01-20Merge tag '2020-01-20-ti-2020.04' of ↵Tom Rini1-2/+1
https://gitlab.denx.de/u-boot/custodians/u-boot-ti K3 J721E: * DMA support. * MMC and ADMA support. * EEPROM support. * J721e High Security EVM support. * USB DT nodes K3 AM654: * Fixed boot due to pmic probe error. * USB support and DT nodes. * ADMA support DRA7xx/AM57xx: * BBAI board support * Clean up of net platform code under board/ti AM33/AM43/Davinci: * Reduce SPL size for omap3 boards. * SPL DT support for da850-lcdk * PLL divider fix for AM335x
2020-01-20clk: sci-clk: add slack to clk-set-rate passed to firmwareLokesh Vutla1-2/+1
Add slack to the clock frequency parameters passed to firmware within clk_set_rate. min-freq is changed to 0 and max-rate is changed to ULONG_MAX. This fixes certain issues with pll clock rounding when the firmware is not able to set the frequency exactly to the target, the current implementation fails if the available frequency is even 1Hz off the target. With the change, the firmware still tries its best to set the frequency as close as possible to the target. Reported-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-17common: Move get_tbclk() to time.hSimon Glass1-0/+1
This function related to timer and most of the timer functions are in time.h, so move this function there. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17common: Move clock functions into a new fileSimon Glass1-0/+1
These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-16clk: mediatek: fix clock-rate overflow problemSam Shih1-3/+3
This patch fix clock-rate overflow problem in mediatek clock driver common part. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: mediatek: add driver for MT7622Sam Shih2-0/+679
This patch add clock driver for MediaTek MT7622 SoC. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2020-01-16clk: fixed_rate: add dummy enable() functionChunfeng Yun1-0/+7
This is used to avoid clk_enable() return -ENOSYS. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: add APIs to get (optional) clock by name without a deviceChunfeng Yun1-0/+28
Sometimes we may need get (optional) clock without a device, that means use ofnode. e.g. when the phy node has subnode, and there is no device created for subnode, in this case, we need these new APIs to get subnode's clock. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: check valid clock by clk_valid()Chunfeng Yun1-8/+8
Add valid check for clk->dev, it's useful when get optional clock even when the clk point is valid, but its dev will be NULL. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: fix error check for devm_clk_get_optional()Chunfeng Yun1-1/+1
If skip all return error number, it may skip some real error cases, so only skip the error when the clock is not provided in DTS Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: mediatek: mt7629: add support for ssusbsysChunfeng Yun1-0/+42
The SSUSB IP's clocks come from ssusbsys module on mt7629, so add its driver Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: mediatek: add configurable pcw_chg_reg/ibits/fmin to mtk_pllmingming lee2-8/+20
Add configurable pcw_chg_reg/ibits/fmin to mtk_pll to support mt8512
2020-01-16clk: mediatek: add set_clr_upd mux type flowmingming lee2-11/+55
Add new set_clr_upd mux type and related operation to mtk common clock driver to support mt8512
2020-01-16clk: mediatek: add driver support for MT8512mingming lee2-0/+874
Add clock driver for MediaTek MT8512 SoC, include topckgen, apmixedsys and infracfg support. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2020-01-14clk: imx: add i.IMXRT1050 clk driverGiulio Benetti3-0/+310
Add i.MXRT1050 clk driver support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14clk: imx: pfd: add set_rate()Giulio Benetti1-0/+22
Implement set_rate() for pfd. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14clk: imx: pllv3: add support for PLLV3_AV typeGiulio Benetti1-0/+76
Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14clk: imx: pllv3: add PLLV3_SYS supportGiulio Benetti1-0/+53
Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14clk: imx: pllv3: add set_rate() supportGiulio Benetti1-0/+27
Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14clk: imx: pllv3: add disable() supportGiulio Benetti1-0/+16
Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14clk: imx: pllv3: add enable() supportGiulio Benetti1-0/+24
Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USBGiulio Benetti1-0/+2
div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocksGiulio Benetti1-5/+15
Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14clk: imx8qxp: extend to support getting I2C IPG clockAnatolij Gustschin1-0/+12
Since commit d02be21d3004 ("i2c: imx_lpi2c: add ipg clk") getting I2C clocks doesn't work. Add I2C IPG clock IDs to related switch statements to fix it. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-01-09Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-mpc83xxTom Rini1-1/+4
- A small PR with MC8309 fixes from Rasmus.
2020-01-09Merge tag 'dm-pull-8jan20' of git://git.denx.de/u-boot-dmTom Rini1-2/+2
dm: Increased separation of ofdata_to_platdata() and probe methods
2020-01-08Merge tag 'efi-2020-04-rc1' of ↵Tom Rini1-0/+1
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-04-rc1 This pull request provides: * support for FIT images for UEFI binaries * drivers for hardware random number generators * an implementation of the EFI_RNG_PROTOCOL * a sub-command for efidebug to display configuration tables
2020-01-08Merge tag 'u-boot-imx-20200108' of ↵Tom Rini4-0/+390
https://gitlab.denx.de/u-boot/custodians/u-boot-imx --------------------------------------------------------------------- Add i.MX8MP SoC and EVK board Update README for i.MX8MN EVK and fix mmc env Add pca9450 driver -------------------------------------------------------------------- Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/634211885
2020-01-08clk: imx: add i.MX8MP clk driverPeng Fan3-0/+380
Add i.MX8MP clk driver for i.MX8MP CLK driver model usage Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08clk: imx: add imx_clk_mux2_flagsPeng Fan1-0/+10
Add imx_clk_mux2_flags which will be used by i.MX8MP Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08mpc83xx_clk: always treat MPC83XX_CLK_PCI as invalidRasmus Villemoes1-1/+4
The current mpc83xx_clk driver is broken for any board for which mpc83xx_has_pci() is true, i.e. anything not MPC8308: When is_clk_valid() reports that MPC83XX_CLK_PCI is valid, init_all_clks() proceeds to call init_single_clk(), but that doesn't know about either MPC83XX_CLK_PCI or has any handling of the TYPE_SCCR_ONOFF mode correctly returned by retrieve_mode(). Hence init_single_clk() ends up returning -EINVAL, and the whole board hangs in serial_init(). The quickest fix is to simply pretend that clock is invalid for all, since nobody can have been relying on it. Adding proper support seems to be a bit more involved than just handling TYPE_SCCR_ONOFF: - The power-on-reset value of SCCR[PCICM] is 0, so mpc83xx_clk_enable() would probably need to be tought to enable the clock. - The frequency of PCI_SYNC_OUT is either SYS_CLK_IN or SYS_CLK_IN/2 depending on the CFG_CLKIN_DIV configuration input, but that can't be read from software, so to properly fill out ->speed[MPC83XX_CLK_PCI] I think one would need guidance from Kconfig or dtb. Partially fixes: 07d538d281 clk: Add MPC83xx clock driver Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Mario Six <mario.six@gdsys.cc>
2020-01-07aspeed: ast2500: Read clock ofdata in the correct methodSimon Glass1-2/+2
At present the clock driver reads its ofdata in the probe() method. This is not correct although it is often harmless. However in this case it causes a problem, something like this: - ast_get_scu() is called (from somewhere) to get the SCI address - this probes the clock - first sets up ofdata (which does nothing at present) - DM marks clock device as active - DM calls pinctrl - pinctrl probes and calls ast_get_scu() in ast2500_pinctrl_probe() - ast_get_scu() probes the clock, but sees it already marked as probed - ast_get_scu() accesses the clock's private data, with scu as NULL - DM calls clock probe function ast2500_clk_probe() which reads scu By putting the read of scu into the correct method, scu is read as part of ofdata setup, and everything is OK. Note: This problem did not matter until now since DM always probed all parents before reading a child's ofdata. The fact that pinctrl is a child of clock seems to trigger this strange bug. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Cédric Le Goater <clg@kaod.org>
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