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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2021-09-30WS cleanup: remove SPACE(s) followed by TABWIP/2021-09-30-whitespace-cleanupsWolfgang Denk1-1/+1
2021-09-30WS cleanup: remove trailing empty linesWolfgang Denk3-3/+0
2021-09-27Merge tag 'dm-pull-next-27sep21' of https://source.denx.de/u-boot/custodians/...WIP/27Sep2021-nextTom Rini9-47/+49
2021-09-27Merge tag 'v2021.10-rc5' into nextTom Rini2-4/+13
2021-09-25clk: Rename clk_get_by_driver_info()Simon Glass1-4/+3
2021-09-25treewide: Try to avoid the preprocessor with OF_REALSimon Glass6-32/+35
2021-09-25treewide: Use OF_REAL instead of !OF_PLATDATASimon Glass6-7/+7
2021-09-25treewide: Simply conditions with the new OF_REALSimon Glass6-12/+12
2021-09-21clk: at91: clk-master: split master clock in pres and dividerClaudiu Beznea4-50/+144
2021-09-17clk: ti: k3: Update driver to account for divider flagsSuman Anna1-2/+2
2021-09-17clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-writeDave Gerlach1-2/+11
2021-09-04mmc: Rename MMC_SUPPORT to MMCSimon Glass1-3/+3
2021-08-25drivers: clk: Add memory clock driver for Intel N5X deviceSiew Chin Lim3-0/+221
2021-08-25drivers: clk: Add clock driver for Intel N5X deviceSiew Chin Lim3-1/+708
2021-08-21clk: clk_versaclock: Add support for versaclock driverAdam Ford3-0/+1110
2021-08-16clk: stm32mp1: add support of BSEC clockPatrick Delaunay1-0/+1
2021-08-12rockchip: px30: Support configure SFCJon Lin1-0/+32
2021-07-27clk: stm32mp1: add support of missing SPI clocksPatrick Delaunay1-0/+13
2021-07-26clk: zynqmp: Add support for enabling clock on lpd_lsbusMichal Simek1-0/+1
2021-07-17Merge tag 'u-boot-imx-20210717' of https://gitlab.denx.de/u-boot/custodians/u...WIP/17Jul2021Tom Rini1-1/+22
2021-07-16Merge branch '2021-07-15-assorted-fixes'Tom Rini1-1/+5
2021-07-16clk: stm32mp1: add support of SYSCFG clockPatrick Delaunay1-0/+1
2021-07-15clk: Detect failure to set defaultsSimon Glass1-1/+5
2021-07-14clk: uniphier: Add PCIe clock entryKunihiko Hayashi1-0/+3
2021-07-10clk: imx8mm: Add SPI clocksFrieder Schrempf1-1/+22
2021-07-08clk: armada-37xx: Set DM_FLAG_PRE_RELOCMarek BehĂșn2-0/+2
2021-07-07Merge tag 'dm-pull-6jul21' of https://source.denx.de/u-boot/custodians/u-boot-dmWIP/07Jul2021Tom Rini1-0/+2
2021-07-06dm: define LOG_CATEGORY for all uclassPatrick Delaunay1-0/+2
2021-07-06drivers: clk: sifive: fu740-prci: replace 'pciaux' with 'pcieaux'Green Wan1-3/+3
2021-07-01Merge tag 'xilinx-for-v2021.10' of https://source.denx.de/u-boot/custodians/u...WIP/01Jul2021-nextTom Rini3-0/+198
2021-06-28Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-sh int...WIP/28Jun2021-nextTom Rini7-0/+371
2021-06-28Merge tag 'v2021.07-rc5' into nextTom Rini1-2/+6
2021-06-24clk: renesas: Add R8A779A0 clock tablesHai Pham7-0/+338
2021-06-24clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock codeMarek Vasut2-0/+33
2021-06-23clk: zynq: Add clock wizard driverZhengxun3-0/+198
2021-06-19Merge tag 'u-boot-rockchip-20210618' of https://source.denx.de/u-boot/custodi...WIP/19Jun2021-nextTom Rini2-0/+2960
2021-06-18clk: cosmetic change in uclassPatrick Delaunay1-1/+1
2021-06-18rockchip: rk3568: add clock driverElaine Zhang2-0/+2960
2021-06-17clk: k210: Move k210 clock out of its own subdirectorySean Anderson5-15/+14
2021-06-17clk: k210: Remove bypass driverSean Anderson2-274/+1
2021-06-17clk: k210: Don't set PLL rates if we are already at the correct rateSean Anderson1-7/+8
2021-06-17clk: k210: Re-add support for setting rateSean Anderson1-5/+84
2021-06-17clk: k210: Implement soc_clk_dumpSean Anderson1-2/+66
2021-06-17clk: k210: Move pll into the rest of the driverSean Anderson3-594/+601
2021-06-17clk: k210: Rewrite to remove CCFSean Anderson3-523/+439
2021-06-17clk: Allow force setting clock defaults before relocationSean Anderson2-11/+18
2021-06-11clk: add support for TI K3 SoC clocksTero Kristo3-0/+387
2021-06-11clk: add support for TI K3 SoC PLLTero Kristo3-0/+296
2021-06-11clk: fix set_rate to clean up cached rates for the hierarchyTero Kristo1-0/+19
2021-06-11clk: fix assigned-clocks to pass with deferring providerTero Kristo1-0/+18