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path: root/drivers/clk/sunxi
AgeCommit message (Expand)AuthorFilesLines
2022-06-26clk: sunxi: Add additional RTC compatible stringsSamuel Holland1-0/+2
2022-05-24clk: sunxi: add and use dummy gate clocksAndre Przywara4-0/+9
2022-05-24clk: sunxi: add PIO bus gate clocksAndre Przywara12-0/+28
2022-05-24clk: sunxi: h6_r: Correct the driver nameSamuel Holland1-2/+2
2022-05-23clk: sunxi: implement clock driver for suniv f1c100sGeorge Hilliard3-0/+82
2021-10-25clk: sunxi: Extend DM_RESET selection to SPLSamuel Holland1-0/+1
2021-10-11clk: sunxi: Add drivers for A31 and H6 PRCM CCUsSamuel Holland4-0/+136
2021-10-11clk: sunxi: Add support for I2C gates/resetsSamuel Holland12-0/+86
2021-10-11clk: sunxi: Move header out of arch directorySamuel Holland13-13/+13
2021-04-16clk: sunxi: h6: Add XHCI clocksSamuel Holland1-0/+2
2021-04-16clk: sunxi: Add a dummy clock driver for the RTCSamuel Holland2-0/+37
2021-01-25clk: sunxi: Add support for H616 clocksJernej Skrabec3-0/+128
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass11-11/+11
2020-11-17clk: sunxi: add compatible string for V3Icenowy Zheng1-0/+2
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass12-0/+12
2020-05-18common: Drop log.h from common headerSimon Glass1-0/+1
2019-07-16sunxi: clocks: Add H6 USB clock gates and resetsAndre Przywara1-0/+29
2019-04-16clk: sunxi: r40: Fix GMAC reset reg offsetJagan Teki1-1/+2
2019-04-01clk: sunxi: a10: Add CLK_AHB_GMACJagan Teki1-0/+2
2019-03-09clk: sunxi: h3: Implement EPHY CLK and RESETJagan Teki1-0/+4
2019-03-09clk: sunxi: Implement EMAC, GMAC clocks, resetsJagan Teki6-0/+15
2019-03-09clk: sunxi: Implement A10 EMAC clocksJagan Teki2-0/+2
2019-03-04clk: sunxi: Implement SPI clocks, resetsJagan Teki11-0/+97
2019-01-30sunxi: clk: enable clk and reset for CCU devicesAndre Przywara1-0/+12
2019-01-29sunxi: clk: A80: add MMC clock supportAndre Przywara1-1/+27
2019-01-29sunxi: clk: add MMC gates/resetsAndre Przywara11-0/+63
2019-01-18clk: sunxi: Add Allwinner A80 CLK driverJagan Teki3-0/+65
2019-01-18clk: sunxi: Add Allwinner H6 CLK driverJagan Teki3-0/+61
2019-01-18clk: sunxi: Implement UART resetsJagan Teki7-0/+43
2019-01-18clk: sunxi: Implement UART clocksJagan Teki9-0/+57
2019-01-18clk: sunxi: Add Allwinner V3S CLK driverJagan Teki3-0/+59
2019-01-18clk: sunxi: Add Allwinner R40 CLK driverJagan Teki3-0/+78
2019-01-18clk: sunxi: Add Allwinner A83T CLK driverJagan Teki3-0/+71
2019-01-18clk: sunxi: Add Allwinner A23/A33 CLK driverJagan Teki3-0/+71
2019-01-18clk: sunxi: Add Allwinner A31 CLK driverJagan Teki3-0/+76
2019-01-18clk: sunxi: Add Allwinner A10s/A13 CLK driverJagan Teki3-0/+64
2019-01-18clk: sunxi: Add Allwinner A10/A20 CLK driverJagan Teki3-0/+67
2019-01-18clk: sunxi: Add Allwinner H3/H5 CLK driverJagan Teki3-0/+87
2019-01-18reset: Add Allwinner RESET driverJagan Teki2-0/+21
2019-01-18clk: Add Allwinner A64 CLK driverJagan Teki4-0/+147