Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2019-07-19 | clk: sifive: Drop GEMGXL clock driver | Anup Patel | 3 | -69/+0 |
2019-07-19 | clk: sifive: Sync-up main driver with upstream Linux | Anup Patel | 1 | -36/+60 |
2019-07-19 | clk: sifive: Sync-up DT bindings header with upstream Linux | Anup Patel | 1 | -1/+1 |
2019-07-19 | clk: sifive: Sync-up WRPLL library with upstream Linux | Anup Patel | 1 | -13/+13 |
2019-07-19 | clk: sifive: Factor-out PLL library as separate module | Anup Patel | 5 | -498/+1 |
2019-06-01 | clk: sifive: Add clock driver for GEMGXL MGMT | Bin Meng | 3 | -0/+69 |
2019-05-09 | clk: sifive: fu540-prci: Change include order | Jagan Teki | 1 | -1/+1 |
2019-02-27 | clk: Add SiFive FU540 PRCI clock driver | Anup Patel | 5 | -0/+1119 |