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path: root/drivers/clk/sifive
AgeCommit message (Expand)AuthorFilesLines
2020-06-04clk: sifive: fu540-prci: Release ethernet clock resetPragnesh Patel1-0/+20
2020-06-04clk: sifive: fu540-prci: Add ddr clock initializationPragnesh Patel1-6/+45
2020-06-04clk: sifive: fu540-prci: Add clock enable and disable opsPragnesh Patel1-12/+96
2020-05-18common: Drop linux/delay.h from common headerSimon Glass1-0/+1
2020-02-05dm: core: Require users of devres to include the headerSimon Glass1-0/+1
2019-07-19clk: sifive: Drop GEMGXL clock driverAnup Patel3-69/+0
2019-07-19clk: sifive: Sync-up main driver with upstream LinuxAnup Patel1-36/+60
2019-07-19clk: sifive: Sync-up DT bindings header with upstream LinuxAnup Patel1-1/+1
2019-07-19clk: sifive: Sync-up WRPLL library with upstream LinuxAnup Patel1-13/+13
2019-07-19clk: sifive: Factor-out PLL library as separate moduleAnup Patel5-498/+1
2019-06-01clk: sifive: Add clock driver for GEMGXL MGMTBin Meng3-0/+69
2019-05-09clk: sifive: fu540-prci: Change include orderJagan Teki1-1/+1
2019-02-27clk: Add SiFive FU540 PRCI clock driverAnup Patel5-0/+1119