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2010-04-13ppc: Move cpu/$CPU to arch/ppc/cpu/$CPUPeter Tyser15-4421/+0
2010-04-0785xx: Added various P1012/P1013/P1021/P1022 definesKumar Gala2-4/+36
2010-04-07fsl-ddr: change the default burst mode for DDR3Dave Liu1-4/+10
2010-04-07fsl-ddr: Fix the turnaround timing for TIMING_CFG_4Dave Liu1-9/+17
2010-01-05fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleaveDave Liu1-0/+3
2010-01-05fsl-ddr: add override for the Rtt_WrDave Liu1-3/+7
2010-01-05fsl-ddr: add the override for write levelingDave Liu2-6/+15
2010-01-05fsl-ddr: Fix power-down timing settingsDave Liu1-3/+4
2010-01-05ppc/8xxx: Remove is_fsl_pci_agentKumar Gala1-41/+3
2010-01-05ppc/8xxx: Don't use pci_cfg on FSL_CORENET platformsKumar Gala1-0/+3
2009-11-12fsl-ddr: Fix the chip-select interleaving issueDave Liu1-4/+3
2009-10-16mpc8xxx: improve LAW error messages when setting up DDRPaul Gortmaker1-4/+5
2009-09-24ppc/p4080: Add various p4080 related defines (and p4040)Kumar Gala1-0/+4
2009-09-15ppc/8xxx: Misc DDR related fixesKumar Gala2-7/+7
2009-09-08ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu().Poonam Aggrwal1-6/+0
2009-09-08ppc/85xx/86xx: Device tree fixup for number of coresPoonam Aggrwal2-0/+56
2009-09-08ppc/85xx,86xx: Handling Unknown SOC versionPoonam Aggrwal1-2/+3
2009-09-08ppc/8xxx: Refactor code to determine if PCI is enabled & agent/hostKumar Gala2-0/+226
2009-09-08ppc/8xxx: Remove ddr_pd_cntl register since it doesn't existKumar Gala1-23/+0
2009-08-2885xx: Added single core members of FSL P1xx/P2xx processors seriesPoonam Aggrwal1-2/+6
2009-08-2885xx: Added P1020 Processor Support.Poonam Aggrwal1-0/+2
2009-08-288xxx: Removed CONFIG_NUM_CPUS from 85xx/86xxPoonam Aggrwal1-34/+59
2009-08-288xxx: Refactored common cpu specific code for 85xx/86xx into one file.Poonam Aggrwal2-0/+131
2009-07-2285xx, 86xx: Add common board_add_ram_info()Peter Tyser2-41/+98
2009-07-01fsl_ddr: Fix DDR3 calculation of rank density with 8GB or moreTimur Tabi1-1/+1
2009-06-12fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BITKumar Gala7-39/+41
2009-03-30fsl-ddr: add the DDR3 SPD infrastructureDave Liu5-46/+754
2009-03-30fsl-ddr: Fix two bugs in the ddr infrastructureDave Liu1-1/+4
2009-02-16fsl-ddr: Allow system to boot if we have more than 4G of memoryKumar Gala1-1/+1
2009-02-16fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controllerKumar Gala1-0/+4
2009-01-23fsl-ddr: use the 1T timing as default configurationDave Liu1-1/+1
2009-01-23fsl-ddr: make the self refresh idle threshold configurableDave Liu1-4/+8
2009-01-23fsl-ddr: clean up the ddr code for DDR3 controllerDave Liu1-11/+13
2009-01-23fsl-ddr: update the bit mask for DDR3 controllerDave Liu1-4/+8
2008-12-03fsl ddr skip interleaving if not supported.Ed Swarthout2-12/+17
2008-10-18Add debug information for DDR controller registersHaiying Wang1-0/+13
2008-10-18Check DDR interleaving modeHaiying Wang2-5/+112
2008-10-18Pass dimm parameters to populate populate controller optionsHaiying Wang4-87/+7
2008-10-18Make DDR interleaving mode work correctlyHaiying Wang2-12/+54
2008-10-18rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD1-7/+7
2008-09-13Coding style cleanup, update CHANGELOGWolfgang Denk1-15/+15
2008-09-07Fix compiler warning in mpc8xxx ddr codeKumar Gala1-2/+4
2008-08-27FSL DDR: Add DDR2 DIMM paramter supportKumar Gala1-0/+339
2008-08-27FSL DDR: Add DDR1 DIMM paramter supportKumar Gala1-0/+343
2008-08-27FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.Kumar Gala9-0/+2418
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