rocket-tools/riscv-gnu-toolchain/qemu/roms/u-boot.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2010-04-13	ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU	Peter Tyser	1	-1366/+0
2010-04-07	fsl-ddr: Fix the turnaround timing for TIMING_CFG_4	Dave Liu	1	-9/+17
2010-01-05	fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave	Dave Liu	1	-0/+3
2010-01-05	fsl-ddr: add override for the Rtt_Wr	Dave Liu	1	-3/+7
2010-01-05	fsl-ddr: add the override for write leveling	Dave Liu	1	-6/+14
2010-01-05	fsl-ddr: Fix power-down timing settings	Dave Liu	1	-3/+4
2009-09-15	ppc/8xxx: Misc DDR related fixes	Kumar Gala	1	-5/+5
2009-09-08	ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist	Kumar Gala	1	-23/+0
2009-06-12	fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT	Kumar Gala	1	-2/+1
2009-03-30	fsl-ddr: add the DDR3 SPD infrastructure	Dave Liu	1	-36/+344
2009-03-30	fsl-ddr: Fix two bugs in the ddr infrastructure	Dave Liu	1	-1/+4
2009-01-23	fsl-ddr: make the self refresh idle threshold configurable	Dave Liu	1	-4/+8
2009-01-23	fsl-ddr: clean up the ddr code for DDR3 controller	Dave Liu	1	-11/+13
2009-01-23	fsl-ddr: update the bit mask for DDR3 controller	Dave Liu	1	-4/+8
2008-10-18	Add debug information for DDR controller registers	Haiying Wang	1	-0/+13
2008-10-18	Make DDR interleaving mode work correctly	Haiying Wang	1	-12/+49
2008-09-07	Fix compiler warning in mpc8xxx ddr code	Kumar Gala	1	-2/+4
2008-08-27	FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.	Kumar Gala	1	-0/+993