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2009-01-2385xx: Introduce CONFIG_SYS_PCI*_IO_VIRT for FSL boardsKumar Gala2-2/+2
Introduce a new define to seperate out the virtual address that PCI IO space is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-2385xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boardsKumar Gala10-28/+28
Introduce a new define to seperate out the virtual address that PCI memory is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-2385xx: Use CONFIG_SYS_{PCI*,RIO*}_MEM_PHYS for physical address on FSL boardsKumar Gala6-9/+9
Use the _MEM_PHYS defines instead of _MEM_BUS for LAW and real address fields of TLBs. This is what we should have always been using from the start. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-2385xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boardsKumar Gala5-15/+15
Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead of _IO_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-2385xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boardsKumar Gala11-39/+39
Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead of _MEM_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-2385xx: separate FLASH BASE virtual from physical addressKumar Gala6-6/+6
Added a CONFIG_SYS_FLASH_BASE_PHYS for use as the physical address and maintain CONFIG_SYS_FLASH_BASE as the virtual address of the flash. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-2385xx: separate PIXIS virtual from physical addressKumar Gala4-4/+4
Added a PIXIS_BASE_PHYS for use as the physical address and maintain PIXIS_BASE as the virtual address of the PIXIS fpga registers. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23microblaze: Change microblaze-generic config fileMichal Simek1-0/+2
Signed-off-by: Michal Simek <monstr@monstr.eu>
2009-01-23microblaze: Rename ml401 to microblaze-genericMichal Simek5-0/+0
Signed-off-by: Michal Simek <monstr@monstr.eu>
2009-01-16Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk11-1018/+534
2009-01-16sh: Fix compile error on lowlevel_init fileNobuhiro Iwamatsu4-8/+13
lowlevel_init of SH was corrected to use the write/readXX macro. However, there was a problem that was not able to be compiled partially. This patch corrected this. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2009-01-16sh: Fix up rsk7203 target for out of tree buildKieran Bingham1-0/+4
Fix up rsk7203 target to build successfully using out-of-tree build. Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2009-01-16sh: use write{8,16,32} in all lowlevel_initJean-Christophe PLAGNIOL-VILLARD10-785/+286
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2009-01-16sh: lowlevel_init coding style cleanupJean-Christophe PLAGNIOL-VILLARD10-634/+640
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2009-01-14ppc4xx: Add loadpci command to esd's CPCI4052 and CPCI405AB boardsMatthias Fuchs1-0/+1
This patch adds esd's loadpci BSP command to CPCI4052 and CPCI405AB board. This requires CONFIG_CMD_BSP and CONFIG_PRAM. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
2009-01-14ppc4xx: Disable pci node in device tree on CPCI405 pci adaptersMatthias Fuchs1-0/+24
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
2009-01-14ppc4xx: Cleanup CPCI405 board codeMatthias Fuchs1-163/+144
This patch cleans up CPCI405 board support: - wrap long lines - unification of spaces in function calls - remove dead code Use correct io accessors on peripherals. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
2009-01-14ppc4xx: Enable auto RS485 mode on PLU405 boardsMatthias Fuchs1-0/+10
This patch turns on the auto RS485 mode in the 2nd external uart on PLU405 boards. This is a special mode of the used Exar XR16C2850 uart. Because these boards only have a 485 physical layer connected it's a good idea to turn it on by default. Signed-off-by: Matthias Fuchs <mf@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
2009-01-14Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk3-12/+13
2009-01-13Some changes of TLB entry setting for MPC8572DSHaiying Wang1-4/+3
- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode, all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0 can not access PIXIS_BASE anymore (any access will cause DataTLBError exception) - Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2009-01-13Change PCIE1&2 deciide logic on MPC8544DS board more readableRoy Zang1-2/+2
The IO port selection for MPC8544DS board: Port cfg_io_ports PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 PCIE2 0x4, 0x5, 0x6, 0x7 PCIE3 0x6, 0x7 This patch changes the PCIE12 and PCIE2 logic more readable. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
2009-01-13PCIE2 and PCIE3 are decided by corresponing bit in devdisr instead of PCIE1 bitRoy Zang1-2/+2
PCIE2 and PCIE3 should be decided by corresponing bit in devdisr instead of PCIE1 bit. On MPC8572DS board, PCIE refers to PCIE1. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
2009-01-13Fix IO port selection issue on MPC8544DS and MPC8572DS boardsRoy Zang2-4/+6
The IO port selection is not correct on MPC8572DS and MPC8544DS board. This patch fixes this issue. For MPC8572 Port cfg_io_ports PCIE1 0x2, 0x3, 0x7, 0xb, 0xc, 0xf PCIE2 0x3, 0x7 PCIE3 0x7 For MPC8544 Port cfg_io_ports PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 PCIE2 0x4, 0x5, 0x6, 0x7 PCIE3 0x6, 0x7 Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
2009-01-13mpc8610hpcd: Fix PCI mapping conceptsBecky Bruce2-8/+8
Rename _BASE to _BUS, as it's actually a PCI bus address, separate virtual and physical addresses into _VIRT and _PHYS, and use each appopriately. This makes the code easier to read and understand, and facilitates mapping changes going forward. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
2009-01-13sbc8641d: Fix PCI mapping conceptsBecky Bruce2-9/+9
Rename _BASE to _BUS, as it's actually a PCI bus address, separate virtual and physical addresses into _VIRT and _PHYS, and use each appopriately. This makes the code easier to read and understand, and facilitates mapping changes going forward. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
2009-01-10Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk13-54/+93
2009-01-07bf537-stamp/nand: fix board_nand_init prototypeMike Frysinger1-1/+3
The board_nand_init() function should return an int, not void. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-07Blackfin: fix out-of-tree building with ldscriptsMike Frysinger8-16/+20
Many of the Blackfin board linker scripts are preprocessed, so make sure we output the linker script into the build tree rather than the source tree. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-07Blackfin: fix linker scripts to work with --gc-sectionsMike Frysinger4-36/+48
Make sure all .text sections get pulled in and the entry point is properly referenced so they don't get discarded when linking with --gc-sections. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-07Blackfin: set proper LDRFLAGS for parallel booting LDRsMike Frysinger4-1/+22
In order to boot an LDR out of parallel flash, the ldr utility needs a few flags to tell it to generate the right header. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-06m501sk: move to the common memory setupJean-Christophe PLAGNIOL-VILLARD2-202/+0
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-01-06at91rm9200: rename lowlevel init value to CONFIG_SYS_Jean-Christophe PLAGNIOL-VILLARD1-67/+67
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-12-2985xx: Enable inbound PCI config cycles for X-ES boards cleanupPeter Tyser1-0/+4
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-12-29XPedite5200 board support cleanupPeter Tyser9-3/+654
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-12-19mpc8xxx: LCRR[CLKDIV] is sometimes five bitsTrent Piepho12-12/+12
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits instead of four. In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It should be safe as the fifth bit was defined as reserved and set to 0. Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-19XPedite5200 board supportPeter Tyser2-5/+101
Initial support for Extreme Engineering Solutions XPedite5200 - a MPC8548-based PMC single board computer. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-12-1985xx: Enable inbound PCI config cycles for X-ES boardsPeter Tyser1-0/+15
Update X-ES Freescale boards to allow inbound PCI configuration cycles when configured as agent/endpoint. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-12-19XPedite5370 board supportPeter Tyser11-0/+1236
Initial support for Extreme Engineering Solutions XPedite5370 - a MPC8572-based 3U VPX single board computer with a PMC/XMC site. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-12-16board/trab/memory.c: Fix compile problems.Wolfgang Denk1-3/+3
Apply changes from commit 44b4dbed to board/trab/memory.c, too. Actually we'd need a major cleanup here - as it turns out, board/trab/memory.c is more or less a verbatim copy of post/drivers/memory.c ... but then, trab is EOL anyway,r so this is not worth the effort. Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-12-16Merge branch 'master' of ssh://gemini/home/wd/git/u-boot/masterWolfgang Denk4-4/+3
2008-12-16trab: make trab_fkt standalone code independent of libgccWolfgang Denk2-1/+8
Use our own local functions in lib_arm/ instead. Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-12-16Coding style cleanup, update CHANGELOG.Wolfgang Denk1-1/+0
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-12-14Fix new found CFG_Jean-Christophe PLAGNIOL-VILLARD3-3/+3
Also fix some minor typos. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-12-13Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2-10/+20
2008-12-13Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2-38/+38
2008-12-10ppc4xx: Disable EEPROM write access on PMC440 boardsMatthias Fuchs1-1/+1
This patch disables EEPROM wrtie access by default on PMC440 board. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
2008-12-10ppc4xx: Fix Ethernet PHY LED configuration on PMC440 boardsMatthias Fuchs1-4/+18
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
2008-12-10sh: r2dplus fix register accessJean-Christophe PLAGNIOL-VILLARD1-1/+1
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-12-10sh: r2dplus/lowlevel_init: coding style fixJean-Christophe PLAGNIOL-VILLARD1-21/+21
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-12-10sh: Migo-R: Update BSC valueNobuhiro Iwamatsu1-16/+16
A value of BSC CS4 was wrong, Fixed it. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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