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2020-01-07imx: sync with kernel device tree for Phycore SoMParthiban Nallathambi1-4/+8
Sync the Linux Kernel 5.4-rc6 device tree for Phytec Phycore SoM and Segin board based on imx6UL and imx6ULL. Changes includes Phytec naming convention for the devicetree files. Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2019-06-11imx: Extend PCL063 support for phyCORE-i.MX6ULL SOMParthiban Nallathambi1-0/+5
Extend PHYTEC phyBOARD-i.MX6UL for phyCORE-i.MX6UL SoM (PCL063) with eMMC on SoM. CPU: Freescale i.MX6ULL rev1.0 792 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 38C Reset cause: POR Model: Phytec phyBOARD-i.MX6ULL-Segin SBC Board: PHYTEC phyCORE-i.MX6ULL DRAM: 256 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial@02020000 Out: serial@02020000 Err: serial@02020000 Net: FEC0 Working: - Eth0 - i2C - MMC/SD - eMMC - UART (1 & 5) - USB (host & otg) Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com>
2019-06-11ARM: dts: i.MX6ULL: U-Boot specific dts for u-boot, dm-splParthiban Nallathambi1-0/+1
u-boot,dm-spl property is specific to U-Boot, so created one for i.MX6ULL platforms. Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com>
2019-01-28imx: Add PHYTEC phyBOARD-i.MX6UL-SeginMartyn Welch1-0/+8
Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on the PHYTEC phyCORE-i.MX6UL SOM (PCL063). CPU: Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 44C Reset cause: POR Board: PHYTEC phyCORE-i.MX6UL I2C: ready DRAM: 256 MiB NAND: 512 MiB MMC: FSL_SDHC: 0 In: serial Out: serial Err: serial Net: FEC0 Working: - Eth0 - i2C - MMC/SD - NAND - UART (1 & 5) - USB (host & otg) Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
generated by cgit v1.1 at 2024-08-01 17:51:39 +0000