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2017-12-06powerpc: mpc85xx: Fix static TLB table for SDRAMYork Sun1-1/+1
Most predefined TLB tables don't have memory coherence bit set for SDRAM. This wasn't an issue before invalidate_dcache_range() function was enabled. Without the coherence bit, dcache invalidation doesn't automatically flush the cache. The coherence bit is already set when dynamic TLB table is used. For some boards with different SPL boot method, or with legacy fixed setting, this bit needs to be set in TLB files. Signed-off-by: York Sun <york.sun@nxp.com>
2017-08-16env: Rename some other getenv()-related functionsSimon Glass1-2/+2
We are now using an env_ prefix for environment functions. Rename these other functions as well, for consistency: getenv_vlan() getenv_bootm_size() getenv_bootm_low() getenv_bootm_mapsize() env_get_default() Suggested-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16env: Rename getenv/_f() to env_get()Simon Glass1-2/+2
We are now using an env_ prefix for environment functions. Rename these two functions for consistency. Also add function comments in common.h. Quite a few places use getenv() in a condition context, provoking a warning from checkpatch. These are fixed up in this patch also. Suggested-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-15env: Add an enum for environment stateSimon Glass1-1/+2
At present we have three states for the environment, numbered 0, 1 and 2. Add an enum to record this to avoid open-coded values. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-06-12powerpc: fsl: Update maintainersYork Sun1-1/+1
Update maintainers for B4860QDS, P1010RDB, P1_TWR, T104xRDB. Signed-off-by: York Sun <york.sun@nxp.com>
2017-04-13board_f: Rename initdram() to dram_init()Simon Glass2-2/+2
This allows us to use the same DRAM init function on all archs. Add a dummy function for arc, which does not use DRAM init here. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Dummy function on nios2] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-05board_f: Drop return value from initdram()Simon Glass2-3/+5
At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-05board_f: Drop board_type parameter from initdram()Simon Glass2-2/+2
It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-01-25powerpc: Drop probecpu() in favour of arch_cpu_init()Simon Glass1-1/+1
To avoid an unnecessary arch-specific call in board_init_f(), rename this function. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-01-24NXP: Introduce board/freescale/common/Kconfig and migrate CHAIN_OF_TRUSTTom Rini1-0/+2
Introduce board/freescale/common/Kconfig so that we have a single place for CONFIG options that are shared between ARM and PowerPC NXP platforms. Cc: York Sun <york.sun@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-04ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLSYork Sun1-2/+2
These two macros are used for the same thing, the total number of DDR controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and merge existing usage. Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-15fsl/board/ddr: optimize board-specific cpo for erratum A-009942Shengzhou Liu1-0/+3
Optimize board-specific cpo for erratum A-009942 on b4860qds, ls1043aqds, ls1043ardb, ls1046aqds, ls1046ardb, ls2080ardb, t102xqds, t102xrdb, t1040qds, t104xrdb, t208xqds, t208xrdb, t4qds, t4rdb boards. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: B4420: Remove macro CONFIG_PPC_B4420York Sun3-6/+6
Replace CONFIG_PPC_B4420 with ARCH_B4420 in Kconfig and clean up existing macros.
2016-11-23powerpc: B4860QDS: Remove macro CONFIG_B4860QDSYork Sun1-1/+2
Use CONFIG_TARGET_B4860QDS instead. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23powerpc: B4420QDS: Split from B4860QDS in KconfigYork Sun1-1/+1
Use TARGET_B4420QDS to simplify Kconfig options. Signed-off-by: York Sun <york.sun@nxp.com>
2016-09-27usb: fsl: Rename fdt_fixup_dr_usbSriram Dash1-1/+1
The function fdt_fixup_dr_usb is specific to fsl/nxp. So, make the function name explicit and rename fdt_fixup_dr_usb into fsl_fdt_fixup_dr_usb. Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
2016-09-23treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada1-1/+1
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-08-02board/freescale: Update MAINTAINERS filesYork Sun1-1/+1
Update maintainers for secure boot targets. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-03freescale: Tweak various Makefiles to remove redundancy, fix aestheticsRobert P. J. Day1-3/+3
No intended functional change, just remove redundancies in some Makefiles, and make whitespace aesthetics uniform. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03board/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl bootShengzhou Liu1-5/+3
We should use unified setup_ddr_tlbs() for spl boot and non-spl boot to make sure 'M' bit is set for DDR TLB to maintain cache coherence. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03powerpc/board: SPL: Enable malloc flag in global data.Sumit Garg1-0/+1
For malloc to work in SPL framework enable GD_FLG_FULL_MALLOC_INIT flag in global data after allocating memory using mem_malloc_init. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-06Use correct spelling of "U-Boot"Bin Meng1-1/+1
Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2016-01-25powerpc: mpc85xx: Move set_liodns, setup_portals to common boot seqPrabhakar Kushwaha1-5/+0
Users migrating Freescale's PowerPC SoC U-Boot code to their custom board, often overlook the need to execute set_liodns() and setup_portals() being called by platform files. So Move set_liodns() and setup_portals() to common u-boot boot sequence Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-19Add more SPDX-License-Identifier tagsTom Rini1-3/+1
In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-14Fix GCC format-security errors and convert sprintfs.Ben Whitten1-4/+4
With format-security errors turned on, GCC picks up the use of sprintf with a format parameter not being a string literal. Simple uses of sprintf are also converted to use strcpy. Signed-off-by: Ben Whitten <ben.whitten@gmail.com> Acked-by: Wolfgang Denk <wd@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-11-19Move console definitions into a new console.h fileSimon Glass1-0/+1
The console includes a global variable and several functions that are only used by a small subset of U-Boot files. Before adding more functions, move the definitions into their own header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-10-29net: Move some header files to include/Shaohui Xie1-1/+1
The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM and PPC, move it out of ppc to include/, and change the path in drivers accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05B4860QDS: Enable enet port as per fsl_b4860_serdes2 string in hwconfigSuresh Gupta1-0/+19
In B4860QDS board SerDes2 lanes EFGH either go to SFP or AMC riser card slot2 so either DTSEC3/DTSEC4 or TGEC1/TGEC2 should be accessible. This Patch enables DTSEC3/DTSEC4 or TGEC1/TGEC2 on bases of user specified string fsl_b4860_serdes2:sfp_amc=amc or fsl_b4860_serdes2:sfp_amc=sfp respectively in hwconfig. Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05powerpc/b4860qds: add workaround for XFIShaohui Xie1-0/+13
XFI does not work stable on current board, it's due to heat sink issue, to make it work stable the board needs additional heat sink, enable two XFI lanes only. Right now we do not have such an erratum for the issue, so use a define CONFIG_SYS_FSL_B4860QDS_XFI_ERR to identify it. The workaround will only be used in XFI protocols and only if the hwconfig indicates that XFI is prefered. A new VSC3308 config function is used instead of re-use the original function, to avoid making the function complex and ugly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05B4860QDS: Enable SFP or AMC on basis of hwconfig stringSuresh Gupta1-8/+33
SerDes2 lanes EFGH either go to SFP or AMC riser card slot2. By default AMC will be configured even if no hwconfig is specified. To enable XFI via SFP use the below hwconfig: fsl_b4860_serdes2:sfp_amc=sfp Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@ffeescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05powerpc/b4860qds: dtb fixup for xfiShaohui Xie1-0/+38
Since xfi has no phy, we delete the property "phy-handle" and use a "fixed-link" property for a xfi port. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05powerpc/b4860qds: add xfi supportShaohui Xie2-7/+39
We need following changes to make xfi work on B4: 1. set cross-point switch VSC3308 to use sfp config when running xfi; 2. add 10G interface check for xfi; 3. set phy address for xfi so the 10G ports can be registered by mdio; Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05B4860: Add alternate LC VCO serdes protocols support in board fileShaveta Leekha1-0/+13
Add the support of newly added LC VCO SerDes protocols for configuration of IDT and VSC crossbar Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05B4860QDS: SGMII related updatesShaveta Leekha1-26/+38
- Enable SGMII support for 0x8d Serdes 2 protocol. - Correct Phy address for DTSECx for 0x8d/0xb2 Serdes 2 protocol. - Updated debug statement - Add Alternate LC VCO protocols(0x8d-->0x8c, 0xb2-->0xb1) - Rename onboard PHY address defines for more readability - Add these new Defines in B4860QDS.h file Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05powerpc/b4860: Enable law creation of MAPLEShaveta Leekha2-3/+8
B4860, B4440, B4420 and B4220 have MAPLE, so enable law creation for them only. Remove static LAW creation for MAPLE. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-21fdt: Allow ft_board_setup() to report failureSimon Glass1-1/+3
This function can fail if the device tree runs out of space. Rather than silently booting with an incomplete device tree, allow the failure to be detected. Unfortunately this involves changing a lot of places in the code. I have not changed behvaiour to return an error where one is not currently returned, to avoid unexpected breakage. Eventually it would be nice to allow boards to register functions to be called to update the device tree. This would avoid all the many functions to do this. However it's not clear yet if this should be done using driver model or with a linker list. This work is left for later. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
2014-09-24MAINTAINERS: comment out blank M: fieldMasahiro Yamada1-1/+1
Since commit ddaf5c8f3030050fcd356a1e49e3ee8f8f52c6d4 (patman: RunPipe() should not pipe stdout/stderr unless asked), Patman spits lots of "Invalid MAINTAINERS address: '-'" error messages for patches with global changes. It takes too long for Patman to process them. Anyway, "M: -" does not carry any important information. Rather, it is just like a place holder in case of assigning a new board maintainer. Let's comment out. This commit can be reproduced by the following command: find . -name MAINTAINERS | xargs sed -i -e '/^M:[[:blank:]]*-$/s/^/#/' Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-13kconfig: remove redundant "string" type in arch and board KconfigsMasahiro Yamada1-3/+0
Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME} are specified in arch/Kconfig. We can delete the ones in arch and board Kconfig files. This commit can be easily reproduced by the following command: find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e ' /config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ { N s/\n[[:space:]]*string// } ' Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-07-30Add board MAINTAINERS filesMasahiro Yamada1-0/+17
We have switched to Kconfig and the boards.cfg file is going to be removed. We have to retrieve the board status and maintainers information from it. The MAINTAINERS format as in Linux Kernel would be nice because we can crib the scripts/get_maintainer.pl script. After some discussion, we chose to put a MAINTAINERS file under each board directory, not the top-level one because we want to collect relevant information for a board into a single place. TODO: Modify get_maintainer.pl to scan multiple MAINTAINERS files. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Suggested-by: Tom Rini <trini@ti.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-07-30kconfig: add board Kconfig and defconfig filesMasahiro Yamada1-0/+15
This commit adds: - arch/${ARCH}/Kconfig provide a menu to select target boards - board/${VENDOR}/${BOARD}/Kconfig or board/${BOARD}/Kconfig set CONFIG macros to the appropriate values for each board - configs/${TARGET_BOARD}_defconfig default setting of each board (This commit was automatically generated by a conversion script based on boards.cfg) In Linux Kernel, defconfig files are located under arch/${ARCH}/configs/ directory. It works in Linux Kernel since ARCH is always given from the command line for cross compile. But in U-Boot, ARCH is not given from the command line. Which means we cannot know ARCH until the board configuration is done. That is why all the "*_defconfig" files should be gathered into a single directory ./configs/. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-07-22powerpc/mpc85xx: Check return value of find_tlb_idxYork Sun1-3/+9
find_tlb_idx() is called in board_early_init_r() on multiple boards. The return value is not checked before being used to disable a TLB. In normal case the return value wouldn't be -1. In case of a mis- configuration during porting to a new board, checking the return value may be helpful to reveal some user errors. Signed-off-by: York Sun <yorksun@freescale.com>
2014-06-05powerpc/B4420: Fixed incomplete handling for 0x9d serdes2poonam aggrwal1-0/+6
Crossbars and IDT were not getting configured for Serdes2 protocol 0x9d for B4420. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-13board/b4qds: VID supportShaveta Leekha1-0/+240
The fuse status register provides the values from on-chip voltage ID efuses programmed at the factory. These values define the voltage requirements for the chip. u-boot reads FUSESR and translates the values into the appropriate commands to set the voltage output value of an external voltage regulator. B4860QDS has a PowerOne ZM7300 programmable digital Power Manager which is programmed as per the value read from the fuses. Reference for this code is taken from t4qds VID implementation. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
2014-04-22board/b4qds:Add support of 2 stage NAND boot-loaderPrabhakar Kushwaha4-3/+135
Add support of 2 stage NAND boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(160KB). This further initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR. Finally SPL transer control to u-boot. Initialise/create followings required for SPL framework - Add spl.c which defines board_init_f, board_init_r - update tlb and ddr accordingly Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22board/b4860qds:Slow MDC clock to comply IEEE specs in PBI configPrabhakar Kushwaha1-0/+3
The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher than 2.5 MHZ. It violates the IEEE specs. So Slow MDC clock to comply IEEE specs Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07powerpc/b4860: Add workaround for errata A006384 and A006475Shaveta Leekha1-0/+193
SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384) and at cold temperatures(A006475), workaround recalibrate the PLLs with some SerDes configuration Both these errata are only applicable for b4 rev1. So, make workaround for these errata conditional, depending upon soc version. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07B4860qds: Set SerDes2 refclk2 at to 156.25MHz for XFI to workShaveta Leekha1-4/+3
Change setting of SerDes2 refclk2 to have the default value as it is coming on board that is 156.25MHz, for XFI to work. Also change PLL_NUM variable to the one defined in config_mpc85xx.h for B4860 and B4420. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-0785xx/b4860: Alternate serdes protocols for B4860/B4420poonam aggrwal2-0/+7
On B4860 and B4420, some serdes protocols can be used with LC VCO as well as Ring VCO options. Addded Alternate options with LC VCO for such protocols. For example protocol 0x2a on srds 1 becomes 0x29 if it is LC VCO. The alternate option has the same functionality as the original option; the only difference being LC VCO rather than Ring VCO. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07board/b4860qds: Add support to make PCIe SATA work on B4860QDSShaveta Leekha1-9/+110
1) SerDes2 Refclks have been set properly to make PCIe SATA to work as it work on SerDes refclk of 100MHz 2) Mask the SerDes's device reset request before changing the Refclks for SerDes1 and SerDes2 for PLL locks to happen properly, device reset request bit unmasked after SerDes refclks configuration Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07board/b4860qds: Add support to make Aurora work on B4860QDSShaveta Leekha2-4/+79
1) Add new SerDes1 protocols having Aurora in them 2) Add VSC cross point connections for Aurora to work with CPRI and SGMIIs 3) Configure VSC crossbar switch to connect SerDes1 lanes to aurora on board, by checking SerDes1 protocols 4) SerDes1 Refclks have been set properly to make Aurora, CPRI and SGMIIs to work together properly Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-08-11 13:09:12 +0000