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2014-08-30arm64: Correct passing of Linux kernel argsTom Rini1-3/+5
The Documentation/arm64/booting.txt document says that pass in x1/x2/x3 as 0 as they are reserved for future use. Signed-off-by: Tom Rini <trini@ti.com>
2014-08-30arm: convert Cygnus and NSP boards to KconfigSteve Rae1-0/+8
Convert the bcm958300k and the bcm958622hr boards from "boards.cfg" to Kconfig. Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30arm: add Cygnus and NSP boardsScott Branden3-0/+67
The bcm_ep board configuration is used by a number of boards including Cygnus and NSP. Add builds for the bcm958300k and the bcm958622hr boards. Signed-off-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30arm: bcmnsp: Add bcmnsp u-architectureScott Branden2-0/+26
Base support for the Broadcom NSP SoC. Based on iproc-common and the SoC specific reset function. Signed-off-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30arm: bcmcygnus: Add bcmcygnus u-architectureScott Branden2-0/+27
Base support for the Broadcom Cygnus SoC. Based on iproc-common and the SoC specific reset function. Signed-off-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30arm: iproc: Initial commit of iproc architecture codeScott Branden8-0/+423
The iproc architecture code is present in several Broadcom chip architectures, including Cygnus and NSP. Signed-off-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30arm: vf610: add NFC clock supportStefan Agner2-0/+15
Add NFC (NAND Flash Controller) clock support and enable them at board initialization time. Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-08-30arm: vf610: add NFC pin muxStefan Agner2-0/+38
Add pin mux for NAND Flash Controller (NFC). NAND can be connected using 8 or 16 data lines, this patch adds pin mux entries for all 16 data lines. Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-08-30ARM: Fix overflow in MMU setupMarek Vasut1-1/+1
The patch fixes a corner case where adding size to DRAM start resulted in a value (1 << 32), which in turn overflew the u32 computation, which resulted in 0 and it therefore prevented correct setup of the MMU tables. The addition of DRAM bank start and it's size can end up right at the end of the address space in the special case of a machine with enough memory. To prevent this overflow, shift the start and size separately and add them only after they were shifted. Hopefully, we only have systems in tree which have DRAM size aligned to 1MiB boundary. If not, this patch would break such systems. On the other hand, such system would be broken by design anyway. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-08-30arm: bcm281xx: Add Ethernet Clock supportJiandong Zheng4-0/+181
Enable Ethernet clock when Broadcom StarFighter2 Ethernet block (CONFIG_BCM_SF2_ETH) is enabled. Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30arm: ep9315: Add .vectors section to lds and remove obsolete ldsSergey Kostanbaev1-58/+0
However ep9315 don't use interrupt vectors during startup, but _startup symbol is used inside uboot to calculate actual monitor size. Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com> Cc: albert.u.boot@aribaud.net
2014-08-30socfpga: initialize designware ethernetPavel Machek2-0/+19
Enable initialization fo designware ethernet controller. With this patch, ethernet works in my configuration, provided I set ethernet address in the environment. Signed-off-by: Pavel Machek <pavel@denx.de>
2014-08-29socfpga: Fix SOCFPGA build error for Altera dev kitChin Liang See4-1/+7
To fix the build error when build for Altera dev kit, not virtual target. At same time, set the build for Altera dev kit as default instead virtual target. With that, U-Boot is booting well and SPL still lack of few drivers. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2014-08-29socfpga: fix clock manager register definitionPavel Machek2-99/+105
Structure defining clock manager hardware was wrong, leading to wrong registers being accessed and hang in MMC init. This fixes structure to match hardware. Signed-off-by: Pavel Machek <pavel@denx.de>
2014-08-29arm: include config.h in arch/arm/lib/vectors.SChristian Riesch1-0/+2
config.h is required for CONFIG_SYS_DV_NOR_BOOT_CFG. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Reported-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Heiko Schocher <hs@denx.de> Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
2014-08-29ARM:asm:io.h use static inlineJeroen Hofstee1-6/+6
When compiling u-boot with W=1 the extern inline void for read* is likely causing the most noise. gcc / clang will warn there is never a actual declaration for these functions. Instead of declaring these extern make them static inline so it is actually declared. cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-08-29Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini12-74/+170
2014-08-29Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini5-20/+5
2014-08-29Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini10-1/+217
2014-08-29Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini19-26/+2265
2014-08-29Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2-284/+351
2014-08-28Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini5-4/+185
2014-08-25ARM: DRA: Enable VTT regulatorLokesh Vutla1-0/+3
DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination and this is controlled by gpio7_11. Configuring gpio7_11. The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards, and left unused on previous boards, so it is safe enough to enable gpio on all DRA7 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-25ARM: DRA7: Enable software leveling for dra7Sricharan R3-68/+32
Currently hw leveling is enabled by default on DRA7/72. But the hardware team suggested to use sw leveling as hw leveling is not characterized and seen some test case failures. So enabling sw leveling on all DRA7 platforms. Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-25keystone2: use EFUSE_BOOTROM information to configure PLLsVitaly Andrianov7-0/+129
This patch reads EFUSE_BOOTROM register to see the maximum supported clock for CORE and TETRIS PLLs and configure them accordingly. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-08-25board/ti/dra7xx: add support for parallel NORpekon gupta1-6/+6
This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM. The Flash device is connected to GPMC controller on chip-select[0] and accessed as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and is CFI compatible. As multiple devices are share GPMC pins on this board, so following board settings are required to detect NOR device: SW5.1 (NAND_BOOTn) = OFF (logic-1) SW5.2 (NOR_BOOTn) = ON (logic-0) /* Active-low */ SW5.3 (eMMC_BOOTn) = OFF (logic-1) SW5.4 (QSPI_BOOTn) = OFF (logic-1) And also set appropriate SYSBOOT configurations: SW3.1 (SYSBOOT[ 8])= ON (logic-1) /* selects SYS_CLK1 speed */ SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */ SW3.3 (SYSBOOT[10])= ON (logic-1) /* wait-pin monitoring = enabled */ SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */ SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */ SW3.6 (SYSBOOT[13])= ON (logic-1) /* device bus-width: 1(x16) */ SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */ SW3.8 (SYSBOOT[15])= ON (logic-1) /* reserved */ Also, following changes are required to enable NOR Flash support in dra7xx_evm board profile:
2014-08-24nios2: remove EPCS driverThomas Chou2-718/+1
The Altera EPCS is SPI flash. We have been using SPI flash driver to access EPCS for years. The old EPCS driver could be removed. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2014-08-24nios2: add generic board supportThomas Chou7-162/+49
This patch implements the generic board init as described in doc/README.generic-board. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com> Reviewed-by: Stefan Roese <sr@denx.de>
2014-08-24nios2: remove obsolete PCI5441 and PK1C20 boardsThomas Chou1-8/+0
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2014-08-24nios2: Fix printf size_t format related warnings (again...)Vasili Galka1-0/+4
When compiling the current code on GCC 4.8.3, the following warnings appear: warning: format '%zu' expects argument of type 'size_t', but argument 2 has type 'long unsigned int' [-Wformat=] There were many mails about such warnings on different architectures. This patch limits itself to the nios2 architecture. The problem is that for the size_t (%zu, %zd, ...) arguments of printf GCC does not verify the type match to size_t type. It verifies the type match to the compiler-defined __SIZE_TYPE__ type. Thus, if size_t is defined different from __SIZE_TYPE__ - warnings inevitably appear. There is a comment by Thomas Chou to the (rejected) patch: http://patchwork.ozlabs.org/patch/272102/ which explains that the older GCC toolchains (gcc-3.4.6 and gcc-4.1.2) expect size_t to be "unsigned long" and the newer expect it to be "unsigned int". Thus, no matter how we define size_t - either way warnings appear when using some GCC version. By rejecting that patch, a choice was made to prefer older GCC versions and leave the warnings when building with the newer toolchains. Personally, I disagree with this choice... In any case, this patch proposes a way to fix the warnings for any GCC version. Just define size_t using the __SIZE_TYPE__ compiler-defined type and the type verification will pass. I tested that this fixes the warning on GCC 4.8.3. I don't have an older toolchain to test with, but __SIZE_TYPE__ was definitely defined in GCC 3.4.6, so it should work there too. Signed-off-by: Vasili Galka <vvv444@gmail.com> Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2014-08-21powerpc: mpc8xx: remove FLAGADM board supportMasahiro Yamada1-4/+0
This board has been orphaned for a while and old enough. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21powerpc: mpc8xx: remove GEN860T, GEN806T_SC board supportMasahiro Yamada1-4/+0
These boards have been orphaned for a while and old enough. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21powerpc: mpc8xx: remove SXNI855T board supportMasahiro Yamada1-4/+0
This board has been orphaned for a while and old enough. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21powerpc: mpc8xx: remove svm_sc8xx boardMasahiro Yamada2-8/+0
This board has been orphaned for a while and old enough. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21powerpc: mpc8xx: remove stxxtc board supportMasahiro Yamada1-4/+0
This board has been orphaned for a while and old enough. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21omap: remove omap5912osk board supportMasahiro Yamada1-4/+0
Emails to the board maintainer "Rishi Bhattacharya <rishi@ti.com>" have been bouncing. Tom suggested to remove this board. Remove also omap1510_udc.c because this is the last board to enable it. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Suggested-by: Tom Rini <trini@ti.com>
2014-08-20Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini3-2/+43
2014-08-20powerpc/mpc85xx: Enabling CPC conditionally based on hwconfig optionsShaveta Leekha1-2/+26
If hwconfig does not contains "en_cpc" then by default all cpcs are enabled If this config is defined then only those individual cpcs which are defined in the subargument of "en_cpc" will be enabled e.g en_cpc:cpc1,cpc2; (this will enable cpc1 and cpc2) or en_cpc:cpc2; (this enables just cpc2) Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-20mx6sxsabresd: Add Ethernet supportFabio Estevam2-0/+11
mx6sxsabresd board has 2 FEC ports, each one connected to a AR8031. Add support for one FEC port initially. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20mx6sx: Adjust enable_fec_anatop_clock() for mx6soloxFabio Estevam1-0/+21
Configure and enable the ethernet clock for mx6solox. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20mx6sxsabresd: Convert to the new Kconfig styleFabio Estevam1-0/+4
mx6sxsabresd was not in the master branch when the conversion to the new Kconfig style happened, so convert it now so that it can build again. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20ARM: mx6: Handle the MMDCx_MDCTL COL field capricesMarek Vasut1-1/+7
The COL field value cannot be easily calculated from the desired column number. Instead, there are special cases for that, see the datasheet, MMDCx_MDCTL field description, field COL . Cater for those special cases. Signed-off-by: Marek Vasut <marex@denx.de>
2014-08-20ARM: mx6: Prevent overflow in DRAM size detectionMarek Vasut1-0/+5
The MX6 DRAM controller can be configured to handle 4GiB of DRAM, but only 3840 MiB of that can be really used. In case the controller is configured to operate a 4GiB module, the imx_ddr_size() function will correctly compute that there is 4GiB of DRAM in the system. Firstly, the return value is 32-bit, so the function will effectively return zero. Secondly, the MX6 cannot address the full 4GiB, but only 3840MiB of all that. Thus, clamp the returned size to 3840MiB in such case. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20ARM: mx5: Fix CHSCCDR nameMarek Vasut1-1/+1
Fix the name of the CCM CHSCCDR register. Signed-off-by: Marek Vasut <marex@denx.de>
2014-08-20mx6: add support of multi-processor commandGabriel Huau5-0/+108
This allows u-boot to load different OS or Bare Metal application on different cores of the i.MX6 SoC. For example: running Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1. Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Stefano Babic <sbabic@denx.de>
2014-08-19ARM: zynq: Remove spl.hMichal Simek3-18/+2
Do not specify own zynq specific SPL macros because there is no need for that. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-19ARM: zynq: Move ps7_init() out of spl.hMichal Simek2-2/+2
Prepare for spl.h removal. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-18ARM: tegra: add Colibri T30 board supportStefan Agner4-0/+103
This adds board support for the Toradex Colibri T30 module. Working functions: - SD card boot - eMMC environment and boot - USB host/USB client (on the dual role port) - Network (via ASIX USB) Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-08-18ARM: tegra: Use mem size from MC rather than ODMDATAStephen Warren1-1/+17
In at least Tegra124, the Tegra memory controller (MC) has a register that controls the memory size. Read this to determine the memory size rather than requiring this to be redundantly encoded into the ODMDATA. This way, changes to the BCT (i.e. MC configuration) automatically updated SW's view of the memory size, without requiring manual changes to the ODMDATA. Future work potentially required: * Clip the memory size to architectural limits; U-Boot probably doesn't and won't support either LPAE or Tegra's "swiss cheese" memory layout, at least one of which would be required for >2GB RAM. * Subtract out any carveout required by firmware on future SoCs. Based-on-work-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-08-18ARM: tegra: Disable VPRBryan Wu5-0/+97
On Tegra114 and Tegra124 platforms, certain display-related registers cannot be accessed unless the VPR registers are programmed. For bootloader, we probably don't care about VPR, so we disable it (which counts as programming it, and allows those display-related registers to be accessed). This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c in Chromium OS U-Boot project. Signed-off-by: Andrew Chew <achew@nvidia.com> Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Signed-off-by: Bryan Wu <pengw@nvidia.com> [acourbot: ensure write went through, vpr.c style changes] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <TWarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-10-01 06:52:54 +0000