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2017-04-08spl: Kconfig: SPL_MMC_SUPPORT depends on GENERIC_MMCAlexandru Gagniuc1-1/+1
spl_mmc.c calls mmc_initialize(). This symbol is provided in drivers/mmc/mmc.c when CONFIG_GENERIC_MMC is enabled. The sunxi Kconfig case is an oddball because it redefines SPL_MMC_SUPPORT. Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> [trini: Update arch/arm/cpu/armv8/zynqmp/Kconfig] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-08stm32f7: enable instruction & data cacheVikas Manocha1-0/+2
It also enables commands for cache enable/disable/status. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-04-08armv7m: add instruction & data cache supportVikas Manocha4-4/+363
This patch adds armv7m instruction & data cache support. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-04-08ARMv8: add GOT sections to the list of sections copiedPhilipp Tomsich1-1/+1
Recent Linux distributions (e.g. Debian 9) include cross-compilers for AArch64, but only for the aarch64-linux-gnu triplet only. It can thus be expected that users will attempt to use the system cross-compiler (instead of an aarch64-elf variant) to compile U-Boot for their ARMv8 target systems. One key differences between an aarch64-linux-gnu and an aarch64-elf compiler are the default settings regarding position-independent: with the aarch64-linux-gnu compiler, the default will create and use the global offset table. This change-set adjusts the list of sections copied on ARMv8 to include the GOT sections. With this added, the list matches the previous setup for AArch32 closely. Note that this is not an 'academic' issue, but was in fact encountered by our QA during testing of the RK3399-Q7 BSP and resulted in an early failure of the SPL stage during FDT setup. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-04-06Remove various unused interrupt related codeTom Rini11-148/+5
With d53ecad92f06 some unused interrupt related code was removed. However all of these options are currently unused. Rather than migrate some of these options to Kconfig we just remove the code in question. The only related code changes here are that in some cases we use CONFIG_STACKSIZE in non-IRQ related context. In these cases we rename and move the value local to the code in question. Fixes: d53ecad92f06 ("Merge branch 'master' of git://git.denx.de/u-boot-sunxi") Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-06Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini20-93/+259
trini: Disable CONFIG_SPL_USE_ARCH_MEMSET on orangepi_2 Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-05board_f: Make relocation functions genericSimon Glass5-49/+2
This header file is used by three archs. It could be used by all of them since relocation is a common function. Move it into a generic file. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-05board_f: Make init_helpers genericSimon Glass3-26/+1
This header file is used by two archs. It could be used by all of them since it allows the cache to be on during relocation. Move it into a generic file. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-05powerpc: Move setup_board_extra() into a PPC fileSimon Glass2-0/+33
We don't need this PPC-specific function in generic code. Move it to the powerpc directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-05Move dram_init_banksize() to a common headerSimon Glass2-2/+0
This is an weak function present on all archs so we should have it in the common header file. Remove it from arch-specific headers and add a function comment. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-05board_f: Drop setup_dram_config() wrapperSimon Glass23-26/+68
By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-05board_f: Drop return value from initdram()Simon Glass7-23/+51
At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-05board_f: Drop board_type parameter from initdram()Simon Glass9-12/+12
It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-05board_f: x86: Use checkcpu() for CPU initSimon Glass9-7/+55
At present we misuse print_cpuinfo() do so CPU init on x86. This is done because it is the next available call after the console is enabled. But several arches use checkcpu() instead. Despite the horrible name (which we can fix), it seems a better choice. Adjust the various x86 CPU implementations to move their init code into checkcpu() and use print_cpuinfo() only for printing CPU info. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-05board_f: powerpc: Make prt_8260_rsr(), prt_8260_clks() privateSimon Glass2-1/+10
Move these two function calls into checkcpu(), which is called on this arch immediately after these two. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-05board_f: sandbox: Move sandbox_early_getopt_check() into misc_init_f()Simon Glass1-0/+5
We don't need a special hook for sandbox as one of the later ones will do just as well. We can print error messages about bad options after we print the banner. In fact, it seems better. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-05board_f: powerpc: Move prt_83xx_rsr() to private codeSimon Glass3-0/+8
This function is called just before checkcpu() on MPX83xx. Move it to the code for that arch. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-05board_f: powerpc: Use timer_init() instead of init_timebase()Simon Glass2-2/+2
There is no good reason to use a different name on PowerPC. Change it to timer_init() like the others. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-05board_f: Remove adjust_sdram_tbs_8xx() from the init sequenceSimon Glass1-30/+33
We can just call this from the only place that needs it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-05board_f: Remove sdram_adjust_866() from the init sequenceSimon Glass1-16/+16
We can just call this from the only function that needs it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-05board_f: powerpc: Rename get_clocks_866() to get_clocks()Simon Glass1-1/+1
We really don't need to have a name like this in the generic init sequence. Use the generic get_clocks() name so that we can merge these two at some point. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-05board_f: x86: Rename x86_fsp_init() to arch_fsp_init()Simon Glass2-4/+1
While x86 is the only user and this could in principle be moved to arch_cpu_init() there is some justification for this being a separate call. It provides a way to handle init which is not CPU-specific, but must happen before the CPU can be set up. Rename the function to be more generic. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-05board_f: sandbox: Move setup_ram_buf() to private codeSimon Glass1-0/+7
There is no need to have this call in the generic init sequence and no other architecture has needed it in the time it has been there. Move it into sandbox's private code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-05OpenRISC: RemoveTom Rini35-2366/+0
The OpenRISC architecture is currently unmaintained, remove. Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-05SPARC: RemoveTom Rini62-10527/+0
The SPARC architecture is currently unmaintained, remove. Cc: Francois Retief <fgretief@spaceteq.co.za> Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-05Blackfin: RemoveTom Rini231-68500/+0
The architecture is currently unmaintained, remove. Cc: Benjamin Matthews <mben12@gmail.com> Cc: Chong Huang <chuang@ucrobotics.com> Cc: Dimitar Penev <dpn@switchfin.org> Cc: Haitao Zhang <hzhang@ucrobotics.com> Cc: I-SYST Micromodule <support@i-syst.com> Cc: M.Hasewinkel (MHA) <info@ssv-embedded.de> Cc: Marek Vasut <marex@denx.de> Cc: Martin Strubel <strubel@section5.ch> Cc: Peter Meerwald <devel@bct-electronic.com> Cc: Sonic Zhang <sonic.adi@gmail.com> Cc: Valentin Yakovenkov <yakovenkov@niistt.ru> Cc: Wojtek Skulski <info@skutek.com> Cc: Wojtek Skulski <skulski@pas.rochester.edu> Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-05Merge git://git.denx.de/u-boot-dmTom Rini2-2/+11
2017-04-05sunxi: Add OrangePi PC 2 initial supportAndre Przywara2-0/+149
The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC. Add a (64-bit only) defconfig defining the required options to build the U-Boot proper. Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi and changing the differing components accordingly. This is a preliminary device tree mostly for U-Boot's own sake, it is expected to be updated once the official DT gets accepted upstream. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [squash the commits, update the commit message] Signed-off-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-05sunxi: introduce Allwinner H5 config optionAndre Przywara1-0/+2
The Allwinner H5 Soc is bascially an H3 with high SRAM and ARMv8 cores. As the peripherals and the pinmuxing are almost identical, we piggy back on the shared MACH_SUN8I_H3_H5 config symbol. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-05sunxi: prepare for sharing MACH_SUN8I_H3 config symbolAndre Przywara7-12/+12
The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-05sunxi: DRAM: add Allwinner H5 supportAndre Przywara2-16/+82
The DRAM controller in the Allwinner H5 SoC is again very similar to the one in the H3 and A64. Based on the existing socid parameter, add support for this controller by reusing the bulk of the code and only deviating where needed. These new bits set or cleared here and there have been mostly found by looking at DRAM register dumps after using the H5 boot0 and comparing them to what we set in the code. So for now it's mostly unclear what those bits actually mean - hence the missing names and comments. Also add the delay line parameters taken from the boot0 and libdram disassembly. Register setup differences between H5 and H3 are courtesy of Jens Kuske. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-05sunxi: provide ARMv8 mem_map for every ARM64 boardAndre Przywara1-1/+1
Every armv8 board needs the memory map, so change the #ifdef to ARM64 to avoid enumerating every single board or SoC. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-05sunxi: Kconfig: introduce CONFIG_SUNXI_HIGH_SRAMAndre Przywara1-1/+1
Traditionally Allwinner SoCs have their boot ROM mapped just below 4GB, while the first SRAM region is mapped at address 0. With the extended physical memory support of the A80 this was changed, so the BROM is now at address 0 and the SRAM region starts right behind this at 64KB. This configuration seems to be called "high SRAM". Instead of enumerating the SoCs which have copied this configuration, let's call a spade a spade and introduce a Kconfig option for this setup. SoCs implementing this (A80, A64 and H5, so far), can then select this configuration. Simplify the config header definition on the way. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-05sunxi: simplify ACTLR.SMP bit set #ifdefAndre Przywara2-4/+5
Instead of enumerating all SoC families that need that bit set, let's just express this more clearly: The SMP bits needs to be set on SMP capable ARMv7 CPUs. It's much easier in Kconfig to express it the other way round, so we use ! CPU_IS_UP and ! ARM64. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-05fsl: ls102x: remove redundant GENERIC_TIMER_CLKAndre Przywara2-2/+2
Some Freescale boards used an extra version of the constant to hold the Generic Timer frequency. This can easily be covered by the now unified COUNTER_FREQUENCY constant, so remove this extra variable from those boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: York Sun <york.sun@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-05ARM: rename CONFIG_TIMER_CLK_FREQ to COUNTER_FREQUENCYAndre Przywara2-3/+3
Many ARMv8 boards define a constant COUNTER_FREQUENCY to specify the frequency of the ARM Generic Timer (aka. arch timer). ARMv7 boards traditionally used CONFIG_TIMER_CLK_FREQ for the same purpose. It seems useful to unify them. Since there are less occurences of the latter version, lets convert all users over to COUNTER_FREQUENCY. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-05sunxi: fix ACTLR.SMP assembly routineAndre Przywara1-1/+2
If we take the liberty to use register r0 to perform our bit set, we should be nice enough to tell the compiler about it. Add r0 to the clobber list to avoid potential mayhem. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Jagan Teki <jagan@openedev.com>
2017-04-04arm: bootm: Add dm_remove_devices_flags() call to announce_and_cleanup()Stefan Roese1-0/+9
This patch adds a call to dm_remove_devices_flags() to announce_and_cleanup() so that drivers that have one of the removal flags set (e.g. DM_FLAG_ACTIVE_DMA_REMOVE) in their driver struct, may do some last-stage cleanup before the OS is started. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-04dm: core: Add flags parameter to device_remove()Stefan Roese1-2/+2
This patch adds the flags parameter to device_remove() and changes all calls to this function to provide the default value of DM_REMOVE_NORMAL for "normal" device removal. This is in preparation for the driver specific pre-OS (e.g. DMA cancelling) remove support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04rockchip: Add support for MiQi rk3288 boardJernej Skrabec4-0/+481
MiQi is rk3288 based development board with 1 or 2 GB SDRAM, 16 GB eMMC, micro SD card interface, 4 USB 2.0 ports, HDMI, gigabit Ethernet and expansion ports. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Eddie Cai <eddie.cai.linux@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04rockchip: cosmetic: Sort RK3288 boardsJernej Skrabec2-51/+51
Sort rk3288 boards in alphabetical order. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Eddie Cai <eddie.cai.linux@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04dts: rk3399: move rockchip, vbus-gpio properties into board-specific filesPhilipp Tomsich2-2/+2
The (shared) rk3399.dtsi had defined the 'rockchip,vbus-gpio' properties for each USB 3.0 controller. As the GPIO usage will vary (e.g. one of those GPIOs shuts down one of the regulators on the RK3399-Q7) between boards, we move this from the shared dtsi into the device tree file for the EVB board which these GPIO definitions match. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoMPhilipp Tomsich2-1/+191
The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04arm64: rockchip: rk3399-puma: add DDR3-1333 timingsPhilipp Tomsich1-0/+1537
For the initial validation of the RK3399-Q7 (Puma), the DDR3 has been clocked at 666MHz (i.e. DDR3-1333) using the same (safe) settings as used in Rockchip's MiniLoader. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04rockchip: rk3399: spl: make SPL boot-order configurable via /chosenPhilipp Tomsich1-0/+99
The RK3399 does not have any boot selection pins and the BootROM probes the boot interfaces using the following boot-order: 1. SPI 2. eMMC (sdhci in DTS) 3. SD card (sdmmc in DTS) 4. USB loader For ease of deployment, the SPL stage should mirror the boot order of the ROM and use the same probing order (assuming that valid images can be detected by SPL) unless instructed otherwise. The boot-order can then be configured via the 'u-boot,spl-boot-order' property in the chosen-node of the DTS. While this approach is easily extensible to other boards, it is only implemented for the RK3399 for now, as the large SRAM on the RK3399 makes this easy to fit the needed infrastructure into SPL and our production setup already runs with DM, OF_CONTROL and BLK in SPL. The new boot-order property is expected to be used in conjunction with FIT images (and all legacy image formats disabled via Kconfig). A boot-sequence with probing and fallthroughs from SPI via eMMC to SD card (i.e. &spiflash, &sdhci, &sdmmc) has been validated on the RK3399-Q7. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com> Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04rockchip: rk3188: Add Radxa Rock boardHeiko Stübner3-0/+394
The Rock is a RK3188 based single board computer by Radxa. Currently it still relies on the proprietary DDR init and cannot use the generic SPL, but at least is able to boot a linux kernel and system up to a regular login prompt. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fix sort order in defconfig, enable CONFIG_SPL_TINY_MEMSET: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-04rockchip: dts: firefly: add usb host power supply nodeEddie Cai1-0/+10
firefly have a usb host. add dts node to provide power supply Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04dts: rk3399: add gmac for the rk3399Philipp Tomsich1-0/+55
This change adds the gmac node (i.e. the GMAC Ethernet controller) as defined in the Linux DTS. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04net: gmac_rockchip: Add support for the RK3399 GMACPhilipp Tomsich2-33/+82
The GMAC in the RK3399 is very similar to the RK3288 variant (i.e. it is a Designware GMAC core and requires similar configuration as the RK3288 to switch it to RGMII and set up the TX/RX delays for Gigabit). The key difference is that the register offsets (within the GRF block) and bit-offsets (within those registers) used to hold the configuration differ between the various RK32/33 CPUs. This change refactors the gmac_rockchip.c driver to use a function table (selected via driver_data) to factor out these differences. Each function's implementation then matches the underlying processor. Some collateral changes are needed in the definitions describing the bits and offsets in the GRF are needed to prefix each set of symbolic constants with the SoC name to avoid name clashes... and in doing so, the shifts for masks and constants have been moved into the header files for readability (and to make it easier to stay below 80 chars). X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed commit message typo s/factor our/factor out/: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-04rockchip: pinctrl: rk3399: add GMAC (RGMII only) supportPhilipp Tomsich2-0/+38
To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this point), we need support for additional pin-configuration. This commit adds the pinctrl support for GMAC in RGMII signalling mode: * adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID * adds the required defines (in the GRF support) for configuring the GPIOC pins for RGMII * configures the RGMII pins (in GPIOC) when requested via pinctrl X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-10-11 05:31:53 +0000