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2023-04-24arm: dts: am3x: Update IOPAD to PADCONF to sync with v6.3-rc6Andrew Davis15-789/+787
Several DTS files have been updated in the Linux kernel with a new PADCONF macro replacing the IOPAD version. Sync for the same here. Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24arm: dts: keystone: Update devicetree header comments to sync with v6.3-rc6Andrew Davis18-86/+35
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24arm: dts: omap5x: Update devicetree header comments to sync with v6.3-rc6Andrew Davis5-13/+7
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24arm: dts: omap4x: Update devicetree header comments to sync with v6.3-rc6Andrew Davis10-21/+13
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24arm: dts: omap3x: Update devicetree header comments to sync with v6.3-rc6Andrew Davis18-80/+30
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24arm: dts: dra7x: Update devicetree header comments to sync with v6.3-rc6Andrew Davis18-92/+34
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24arm: dts: dm8x: Update devicetree header comments to sync with v6.3-rc6Andrew Davis7-32/+8
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24arm: dts: am57x: Update devicetree header comments to sync with v6.3-rc6Andrew Davis10-37/+17
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24arm: dts: am43x: Update devicetree header comments to sync with v6.3-rc6Andrew Davis6-29/+11
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24arm: dts: am3x: Update devicetree header comments to sync with v6.3-rc6Andrew Davis19-74/+26
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-23Merge tag 'u-boot-rockchip-20230421' of ↵WIP/23Apr2023Tom Rini29-252/+636
https://source.denx.de/u-boot/custodians/u-boot-rockchip - Add rk3588 evb support; - Update pinctrl for rk3568 and rk3588; - Update rk3288 dts; - Update mmc support for rk3568 and rk3588; - Add rng support for rk3588; - Add DSI support for rk3568; - Some other misc fixes in dts, config, driver;
2023-04-22Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini21-50/+1373
* Add StarFive VisionFive v2 Board support * Support CONFIG_REMAKE_ELF * Code cleanups for RISC-V architecture
2023-04-22Merge tag 'u-boot-stm32-20230419' of ↵Tom Rini2-2/+50
https://source.denx.de/u-boot/custodians/u-boot-stm configs: _ Add usb_pgood_delay for ST boards _ increase malloc size for pre-reloc for stm32mp15 _ Set CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2s for stm32mp15 dts: _ Add QSPI support on STM32MP13x SoC family _ Add FMC support on STM32MP13x SoC family drivers/machine: _ pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing() _ spi: stm32_qspi: Remove useless struct stm32_qspi_flash _ rawnand: stm32_fmc2: remove unsupported EDO mode _ stm32mp: fix various array bounds checks
2023-04-21arm: dts: rockchip: radxa-cm3-io, rock-3a: enable regulators for usbFUKAUMI Naoki2-0/+12
enable regulators for usb host function Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21rockchip: rk3588-rock-5b: Include eMMC node in SPL dtbJonas Karlman2-2/+14
Add sdhci node to SPL and u-boot,spl-boot-order. Also add more supported mmc modes and pinctrl. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21rockchip: rk3568-rock-3a: Enable support for more eMMC modesJonas Karlman1-0/+8
Add supported mmc modes to rk3568-rock-3a device tree. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21ARM: dts: rockchip: rk3588s-u-boot: Add rng nodeChris Morgan1-0/+6
Add a node for the trng found on RK3588 SoCs. Changes in V3: - Added Reviewed-By tag. Changes in V2: - None Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
2023-04-21rockchip: rk3588: Sync sdmmc node from linux-nextJonas Karlman5-18/+30
Sync the sdmmc node from linux-next, include required nodes in SPL and imply Kconfig options required for functional sdmmc clk in SPL and U-Boot proper. This make it possible for both SPL and U-Boot proper to configure sdmmc clocks. In SPL, before TF-A is loaded, scru regs is configured, in U-Boot proper a SCMI message is sent to TF-A. Fixes: 95c8656b72dc ("ARM: dts: rockchip: rk3588s-u-boot: Add sdmmc node") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21rockchip: rk3588: Add support for sdmmc clocks in SPLJonas Karlman2-2/+18
Booting from sdmmc on RK3588 currently works because of a workaround in the device tree, clocks are reordered so that the driver use ciu-sample instead of ciu, and the BootRom initializes sdmmc clocks before SPL is loaded into DRAM. The sdmmc clocks are normally controlled by TF-A using SCMI. However, there is a need to control these clocks in SPL, before TF-A has started. This adds a rk3588_scru driver to control the sdmmc clocks in SPL before TF-A has started, using scru regs. It also adds a small glue driver to bind the scmi clock node to the rk3588_scru driver in SPL. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21rockchip: rk35xx: Enable fdtoverlay and kernel compressionJonas Karlman1-0/+2
Add fdtoverlay_addr_r, kernel_comp_addr_r and imply use of OF_LIBFDT_OVERLAY on RK3568 and RK3588 to support fdtoverlay and kernel compression. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-21rockchip: rk35xx: Fix boot with a large fdt blobJonas Karlman1-0/+2
The TF-A blobs used to boot RK3568 and RK3588 boards is based on atf v2.3. Mainline atf v2.3 contains an issue that could lead to a crash when it fails to parse the fdt blob being passed as the platform param. An issue that was fixed in atf v2.4. The vendor TF-A seem to suffer from a similar issue, and this prevents booting when fdt blob is large enough to trigger this condition. Fix this by implying SPL_ATF_NO_PLATFORM_PARAM to let u-boot pass a NULL pointer instead of the fdt blob as the platform param. This fixes booting Radxa ROCK 3A after recent sync of device tree. Fixes: 073d911ae64a ("rockchip: rk3568-rock-3a: Sync device tree from linux") Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-04-21rockchip: rk3588-rock-5b: Fix sdmmc bootJonas Karlman1-1/+2
Running U-Boot from a SD-card on ROCK 5 Model B fails to load atf using DMA and prints debug_uart messages. <debug_uart> <debug_uart> U-Boot SPL 2023.04-rc3 (Mar 12 2023 - 00:30:16 +0000) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256 error! Bad hash value for 'hash' hash node in 'atf-1' image node mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### Use fifo-mode to disable DMA in SPL, add same-as-spl to boot-order and remove DEBUG_UART_ANNOUNCE option to fix this. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21rockchip: misc: fix misc_read() return checkJohn Keeping1-1/+1
misc_read() is documented to return the number of bytes read or a negative error value. The Rockchip drivers currently do not implement this correctly and instead return zero on success or a negative error value. In preparation for fixing the drivers, fix the condition here to only error on negative values. Suggested-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21arm: dts: rockchip: sync rk3066/rk3188 DT files from linux-next v6.2-rc4Johan Jonker6-26/+68
Sync rk3066/rk3188 DT files from Linux. This is the state as of linux-next v6.2-rc4. New nfc node for MK808 rk3066a. CRU nodes now have a clock property. To prefend dtoc errors a fixed clock must also be included for tpl/spl in the rk3xxx-u-boot.dtsi file. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21arm: dts: rockchip: rk3188-u-boot: add gpio-rangesJohan Jonker1-0/+13
The gpio node names are made generic, but without gpio bank ID. Add gpio-ranges to rk3188-u-boot.dtsi for now till a better method is found. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21arm: dts: rockchip: rk3066a-u-boot: add gpio-rangesJohan Jonker1-0/+25
The gpio node names are made generic, but without gpio bank ID. Add gpio-ranges to rk3066a-u-boot.dtsi for now till a better method is found. Disable gpio6 as the driver gives an error code on return as status. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21arm: dts: rockchip: rk3288: partial sync pwm nodesJohan Jonker1-13/+5
In order to better compare the Linux rk3288.dtsi version 6.3 -rc2 with the U-Boot version partial sync the pwm nodes. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21arm: dts: rockchip: rk3288: partial sync vop/lvds/mipi/hdmi nodesJohan Jonker1-24/+24
In order to better compare the Linux rk3288.dtsi version 6.3 -rc2 with the U-Boot version partial sync the vop/lvds/mipi/hdmi nodes. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21arm: dts: rockchip: rk3288: partial sync edp nodeJohan Jonker2-6/+16
The rk3288 edp node has a phy node in Linux with a clock property while current U-Boot driver expects this clock on position index 1. Move U-Boot-specific DT clock properties to rk3288-u-boot.dtsi and partially sync the edp node. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21arm: dts: rockchip: rk3288: partial sync grf and pmu nodesJohan Jonker1-96/+173
In order to better compare the Linux rk3288.dtsi version 6.3 -rc2 with the U-Boot version partial sync the grf and pmu nodes. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21arm: dts: rockchip: rk3288: move io-domains nodesJohan Jonker5-62/+58
In order to better compare the Linux rk3288.dtsi version with the U-Boot version move the io-domains nodes. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: John Keeping <john@metanate.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21rockchip: rk3288: Use ft_system_setup instead of ft_board_setupJohn Keeping2-2/+2
ft_board_setup() should be availble for use in board files but using it in the rk3288 machine file blocks this functionality. ft_system_setup() is the more appropriate function to use in a machine definition. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21rockchip: Use an external TPL binary on RK3588Jonas Karlman1-1/+1
There is no support to initialize DRAM on RK3588 SoCs using U-Boot TPL and instead an external TPL binary must be used to generate a bootable u-boot-rockchip.bin image. Enable ROCKCHIP_EXTERNAL_TPL by default for RK3588, add build steps for RK3588 to documentation and clean up CONFIG_BINMAN_FDT options. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Jagan Teki <jagan@edgeble.ai>
2023-04-21board: rockchip: Add rk3588 evbKever Yang4-0/+158
rk3588 evb1 v10 is a evalution board from Rockchip, it is a dev board for rockchip and also a reference board for board vendors. Hardware: SoC: RK3588 DRAM: LPDDR4X 8GB Debug: UART2 via USB PCIe: 3x4 *1 SATA *2 HDMI out *2 HDMI IN *1 USB2.0 Host *2 USB3.0 Host *1 Type C *1 MIPI DSI panel dts Sync from Linux v6.2. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@edgeble.ai>
2023-04-20riscv: Support CONFIG_REMAKE_ELFSamuel Holland1-0/+2
Add flags to tell objcopy what kind of ELF to create. Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-04-20riscv: Update alignment for some sections in linker scriptsBin Meng2-4/+4
Some sections in the linker scripts are aligned to 4 bytes, which may cause misaligned exception on some platforms, e.g.: clearing the bss section on 64-bit hardware if __bss_start does not start from a naturally 8 bytes aligned address. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-04-20riscv: spl: Remove relocation sectionsBin Meng2-25/+2
U-Boot SPL is not relocable. Drop these relocation sections. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-04-20riscv: Avoid updating the link registerBin Meng1-1/+1
board_init_r does not return for U-Boot SPL hence there is no need to update the link register when jumping to board_init_r. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-04-20riscv: Change to use positive offset to access relocation entriesBin Meng1-12/+7
The codes currently skip the very first relocation entry, and have an inaccurate comment "skip first reserved entry" indicating that the first entry is reserved, but later it references the elements in the first relocation entry using a minus offset. Change to use a positive offset so that there is no need to skip the first relocation entry. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-04-20riscv: Optimize loading relocation typeBin Meng1-1/+0
't5' already contains relocation type so don't bother reloading it. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-04-20riscv: Optimize source end address calculation in start.SBin Meng1-3/+1
The __bss_start is the source end address hence load its address directly into register 't2' for optimization. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-04-20riscv: Enforce DWARF4 outputBin Meng1-2/+1
Since commit 409e4b547872 ("Makefile: Enforce DWARF4 output") the whole U-Boot build switched to enforce DWARF4 output, but RISC-V is still on its own setting. Let's switch to use U-Boot's setting. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-04-20riscv: Correct a comment in io.hBin Meng1-1/+1
Replace NDS32 with RISC-V in the comments. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-04-20riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device treeYanhong Wang6-1/+483
Add initial device tree for StarFive VisionFive v2 board. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20riscv: dts: jh7110: Add initial u-boot device treeYanhong Wang1-0/+99
Add initial u-boot device tree for the JH7110 RISC-V SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20riscv: dts: jh7110: Add initial StarFive JH7110 device treeYanhong Wang1-0/+573
Add initial device tree for the JH7110 RISC-V SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to KconfigYanhong Wang1-0/+5
Add board support for StarFive VisionFive v2. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoCYanhong Wang1-0/+28
Add Kconfig to select the basic functions for StarFive JH7110 SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20riscv: cpu: jh7110: Add support for jh7110 SoCYanhong Wang6-0/+166
Add StarFive JH7110 SoC to support RISC-V arch. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Reviewed-by: Rick Chen <rick@andestech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-19stm32mp: fix various array bounds checksRasmus Villemoes1-2/+2
In all these cases, the index on the LHS is immediately afterwards used to access the array appearing in the ARRAY_SIZE() on the RHS - so if that index is equal to the array size, we'll access one-past-the-end of the array. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
generated by cgit v1.1 at 2024-07-15 20:21:03 +0000