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2020-12-13dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass7-21/+21
Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass22-36/+36
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass20-24/+24
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: Remove uses of device_bind_offset()Simon Glass1-1/+1
This function is not needed since the standard device_bind() can be used instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Rename device_bind() to device_bind_offset()Simon Glass1-1/+1
This function is not necessary anymore, since device_bind_ofnode() does the same thing and works with both flattree and livetree. Rename it to indicate that it is special. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13test: unit test for exception commandHeinrich Schuchardt1-0/+1
Test that an exception SIGILL is answered by a reset on the sandbox if CONFIG_SANDBOX_CRASH_RESET=y or by exiting to the OS otherwise. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-12-13sandbox: add handler for exceptionsHeinrich Schuchardt4-0/+88
Add a handler for SIGILL, SIGBUS, SIGSEGV. When an exception occurs print the program counter and the loaded UEFI binaries and reset the system if CONFIG_SANDBOX_CRASH_RESET=y or exit to the OS otherwise. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-12-04bootm: Support string substitution in bootargsSimon Glass1-0/+1
In some cases it is necessary to pass parameters to Linux so that it will boot correctly. For example, the rootdev parameter is often used to specify the root device. However the root device may change depending on whence U-Boot loads the kernel. At present it is necessary to build up the command line by adding device strings to it one by one. It is often more convenient to provide a template for bootargs, with U-Boot doing the substitution from other environment variables. Add a way to substitute strings in the bootargs variable. This allows things like "rootdev=${rootdev}" to be used in bootargs, with the ${rootdev} substitution providing the UUID of the root device. For example, to substitute the GUID of the kernel partition: setenv bootargs "console=/dev/ttyS0 rootdev=${uuid}/PARTNROFF=1 kern_guid=${uuid}" part uuid mmc 2:2 uuid bootm This is particularly useful when the command line from another place. For example, Chrome OS stores the command line next to the kernel itself. It depends on the kernel version being used as well as the hardware features, so it is extremely difficult to devise a U-Boot script that works on all boards and kernel versions. With this feature, the command line can be read from disk and used directly, with a few substitutions set up. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-04x86: zimage: Add silent-console processingSimon Glass1-0/+14
At present zimage does its own command-line processing and does not support the 'silent console' feature. There doesn't seem to be any good reason for this. Add support for silent console to zimage. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-04bootm: Add tests for fixup_silent_linux()Simon Glass1-0/+1
This function currently has no tests. Export it so that we can implement a simple test on sandbox. Use IS_ENABLED() to remove the unused code, instead #ifdef. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-04board: sl28: add OP-TEE Trusted OS support (bl32)Michael Walle1-0/+36
Add support to load the OP-TEE Trusted OS by the SPL. Signed-off-by: Michael Walle <michael@walle.cc>
2020-12-04board: sl28: add ATF support (bl31)Michael Walle1-1/+40
Add support to load the bl31 part of the ARM Trusted Firmware by the SPL. Signed-off-by: Michael Walle <michael@walle.cc>
2020-12-04board: sl28: remove u-boot from loadable DT nodeMichael Walle1-3/+0
It is not needed. Remove it. Signed-off-by: Michael Walle <michael@walle.cc>
2020-12-04armv8: layerscape: don't initialize GIC in SPLMichael Walle1-0/+2
The BL31 expects the GIC to be uninitialized. Thus, if we are loading the BL31 by the SPL we must not initialize it. If u-boot is loaded by the SPL directly, it will initialize the GIC again (in the same lowlevel_init()). This was tested on a custom board with SPL loading the BL31 and jumping to u-boot as BL33 as well as loading u-boot directly by the SPL. In case the ATF BL1/BL2 is used, this patch won't change anything, because no SPL is used at all. Signed-off-by: Michael Walle <michael@walle.cc>
2020-12-04treewide: use CONFIG_IS_ENABLED() for ARMV8_SEC_FIRMWARE_SUPPORTMichael Walle5-10/+10
There is SPL_ARMV8_SEC_FIRMWARE_SUPPORT and ARMV8_SEC_FIRMWARE_SUPPORT. Thus use CONFIG_IS_ENABLED() instead of the simple #ifdef. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Michal Simek <michal.simek@xilinx.com>
2020-12-01IPQ40xx: clk: add USB clock handlingRobert Marko1-0/+8
USB clocks were completely forgotten as driver would always return 0 even if clock ID was unknown. This behaviour changed with "IPQ40xx: clk: dont always return 0" and this will now causes the USB-s to fail probing as clock enable will return -EINVAL. So to fix that lets add all of the USB clocks to the driver. Fixes: 430e1dcf ("IPQ40xx: Add USB nodes") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-12-01IPQ40xx: clk: dont always return 0Robert Marko1-2/+2
Currently the driver will go through the clock ID-s and set/enable them as needed. But if the ID is unknown it will fall through the switch case to the default case which will always return 0. This is not correct and default cases should return a error code since clock ID is unknown. So lets return -EINVAL instead. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-12-01IPQ40xx: clk: drop breaks in switch caseRobert Marko1-3/+0
There is no point in having break statements in the switch case as there is already a return before break. So lets drop them from the driver. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-12-01IPQ40xx: clk: use dev_read_addr()Robert Marko1-2/+2
Lets convert the driver to use dev_read_addr() instead of the devfdt_get_addr(). While we are here, lets also alphabetise the includes. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-11-28riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controllerPragnesh Patel1-0/+2
Enable support for SiFive FU540 Opencores I2C master controller. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-11-25remoteproc: stm32: use reset for hold bootPatrick Delaunay1-0/+7
Use the reset function to handle the hold boot bit in RCC with device tree handle with MCU_HOLD_BOOT identifier. This generic reset allows to remove the two specific properties: - st,syscfg-holdboot - st,syscfg-tz This patch prepares alignment with kernel device tree. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Cc: Fabien DESSENNE <fabien.dessenne@st.com> Cc: Arnaud POULIQUEN <arnaud.pouliquen@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-25SPL: stm32mp1: fix spl_mmc_boot_partition not definedRichard Genoud1-0/+2
spl_mmc_boot_partition is only defined when CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION is defined. Signed-off-by: Richard Genoud <richard.genoud@posteo.net> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25ARM: dts: stm32: Drop QSPI CS2 on DHCOMMarek Vasut1-11/+2
The QSPI CS2 is not used on DHCOM, remove the pinmux and flash@1. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25ARM: dts: stm32: Fix uSD card-detect GPIO on DHCOMMarek Vasut1-1/+1
The uSD slot card-detect GPIO is connected to PG1, fix it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25ARM: dts: stm32: Add DHCOM based PicoITX boardMarek Vasut3-0/+108
Add DT for DH PicoITX unit, which is a bare-bones carrier board for the DHCOM. The board has ethernet port, USB, CAN, LEDs and a custom board-to-board expansion connector. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25arm: stm32mp: correct the ALIGN macro usagePatrick Delaunay1-2/+2
Correct the ALIGN macro usage in mmu_set_region_dcache_behaviour call: the address must use ALIGN_DOWN and size can use ALIGN macro. With STM32_SYSRAM_BASE=0x2FFC0000 and MMU_SECTION_SIZE=0x100000 for STM32MP15x the computed address was 30000000 instead of 2ff00000. Fixes: 43fe9d2fda24 ("stm32mp1: mmu_set_region_dcache_behaviour") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25ARM: dts: stm32: Fix typo in stm32h7-u-boot.dtsiPatrice Chotard1-1/+1
Fix typo "firsct" Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25ARM: dts: stm32: Fix timer initialization for stm32 MCU's boardPatrice Chotard5-12/+24
Commit 4b2be78ab66c ("time: Fix get_ticks being non-monotonic") puts in evidence that get_ticks is called before timer initialization. Fix it by initializing timer before relocation. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25ARM: dts: stm32: DT sync with kernel v5.10-rc1 for MCU's boardsPatrice Chotard22-100/+308
Device tree alignment with kernel v5.10-rc1. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25ARM: dts: sync armv7-m.dtsi with kernel v5.10-rc1Patrice Chotard1-3/+1
Since kernel v4.8-rc1, commit 05b23ebc2bd9 ("ARM: dts: armv7-m: remove skeleton.dtsi include"), skeleton.dtsi file is no more included. This synchronization is needed to avoid to get 2 memory node in DTB file if, in DTS file, memory node is declared with the correct syntax as following: memory@90000000 { device_type = "memory"; reg = <0x90000000 0x800000>; }; Then in DTB, we will have the 2 memory nodes, which is incorrect and cause misbehavior during DT parsing by U-boot: memory { device_type = "memory"; reg = <0x00 0x00>; }; memory@90000000 { device_type = "memory"; reg = <0x90000000 0x800000>; }; Issue found when synchronizing MCU's STM32 DT from kernel v5.10-rc1. When using fdtdec_setup_mem_size_base() or fdtdec_setup_memory_banksize() API, first above memory node is found (with reg = <0x00 0x00>), so gd->ram_size, gd->ram_base, gd->bd->bi_dram[bank].start and gd->bd->bi_dram[bank].size are all set to 0 which avoid boards to boot. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-22pinctrl: renesas: r8a77951: Add R8A774E1 PFC supportBiju Das1-0/+1
Renesas RZ/G2H (r8a774e1) is pin compatible with R-Car H3 (r8a77951), however it doesn't have several automotive specific peripherals. Add a r8a77951 specific pin groups/functions along with common pin groups/functions for supporting both r8a77951 and r8a774e1 SoC. PFC changes are synced from mainline linux-5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-11-22pinctrl: renesas: r8a77965: Add R8A774B1 PFC supportBiju Das1-0/+1
Renesas RZ/G2N (r8a774b1) is pin compatible with R-Car M3-N (r8a77965), however it doesn't have several automotive specific peripherals. Add a r8a77965 specific pin groups/functions along with common pin groups/functions for supporting both r8a77965 and r8a774b1 SoC. PFC changes are synced from mainline linux-5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-11-20arm64: zynqmp: Get rid of unused macrosMichal Simek1-4/+2
There is no reason to have these macros. But record offsets of missing register in the structure for future use. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-11-20microblaze: Enable GCC garbage collector for full U-BootMichal Simek2-3/+6
GCC's garbage collector works for Microblaze for quite a long time but none has enabled it. The same change has be done for example by commit fac4790491f6 ("arc: Eliminate unused code and data with GCC's garbage collector"). Before: text data bss dec hex filename 588760 33592 39192 661544 a1828 u-boot After: text data bss dec hex filename 504504 32164 38608 575276 8c72c u-boot Which saves almost 15% of memory footprint. Also group symbols/functions to proper section. Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-11-17sunxi: dts: sync Allwinner V3s-related DTs from Linux 5.10-rc1Icenowy Zheng6-30/+725
This commit imports device tree files that are related to Allwinner V3 series from Linux commit 3650b228f83a ("Linux 5.10-rc1"). Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-11-17sunxi: allow to use AXP20[39] attached to I2C0 on V3 seriesIcenowy Zheng1-0/+1
The reference design of Allwinner V3 series uses an AXP203 or AXP209 PMIC attached to the I2C0 bus of the SoC, although the first community-available V3s board, Lichee Pi Zero, omitted it. Allow to introduce support for the PMIC on boards with it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-11-17sunxi: add V3/S3 supportIcenowy Zheng1-2/+1
Allwinner V3/Sochip S3 uses the same die with Allwinner V3s/S3L, but V3 comes with no co-packaged DDR (DDR3 is usually used externally), and S3L comes with co-packaged DDR3. Add support for Allwinner V3/S3 chips by add SoC names to original V3s choice, and allow to select DDR3. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-11-17sunxi: DT: A64: update device tree filesSamuel Holland25-631/+2383
Import updated device trees from Linux tag v5.9. This picks up new hardware (PinePhone, PineTab); and it drops the U-Boot specific DTSI files for the Pinebook and the Teres-I, since the ANX6345 bridge is now supported upstream. A couple of headers needed updates for recently-added hardware support. Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-11-17sunxi: board: Add PinePhone DT selection logicSamuel Holland1-0/+7
There are two different publicly-released revisions of the PinePhone hardware, versions 1.1 and 1.2; and they need different device trees. Since some GPIO pins were rerouted, we can use that to distinguish between them. Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-11-16Merge tag 'ti-v2021.01-rc3' of ↵Tom Rini4-1/+259
https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Fix Nokia RX-51 boot issues - Fix CONFIG_LOGLEVEL on K3 devices - Add phyBOARD REGOR support
2020-11-16Merge tag 'u-boot-amlogic-20201116' of ↵Tom Rini8-97/+30
https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - Clock fix MMC driver for SM1 based platforms - sync SOC Ids from Linux 5.10-rc1 - fix potential build warning on meson_dw_hdmi and meson-g12a-usb2 phy
2020-11-15ARM: am335x: Add phyBOARD REGOR supportParthiban Nallathambi4-1/+259
phyBOARD-REGOR is based on phyCORE AM335x R2 SoM (PCL060). CPU : AM335X-GP rev 2.1 Model: Phytec AM335x phyBOARD-REGOR DRAM: 512 MiB NAND: 512 MiB MMC: OMAP SD/MMC: 0 eth0: ethernet@4a100000 Working: - Eth0 - i2C - MMC/SD - NAND - UART - USB (host) Device trees were taken from Linux mainline: commit c4d6fe731176 ("Linux 5.9.0") Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2020-11-13rockchip: Enable BINMAN for boards enable SPL_OPTEEKever Yang1-1/+1
Rockchip has many 32bit SoCs and some of them are support SPL_OPTEE now, only boards with SPL_OPTEE support can fit BINMAN well, other boards will fail at initr_binman() in U-Boot proper after below patch, eg. rv1108 board. 83187546ae binman: Support multiple images in the library Fixes: 79030a4861 ("rockchip: Add Single boot image (with binman, pad_cat)") Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-11-13rockchip: rockpro64: fix boot from SPI flash on spi1Hugh Cole-Baker1-4/+0
Commit c4cea2bbf995 ("rockchip: Enable building a SPI ROM image on bob") added an alias spi1 referring to spi@ff1d0000, however there was already an alias spi0 referring to the same node in rockpro64's u-boot.dtsi, and having both aliases present broke booting from SPI flash for this board. Remove the spi0 alias, set the default bus for SPI flash to 1, and enable support for numbered aliases in SPL so that it uses the same bus numbering as U-Boot proper. This fixes booting from U-Boot in SPI flash on the rockpro64 board. Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com> Suggested-by: Simon Glass <sjg@chromium.org> Fixes: c4cea2bbf995 ("rockchip: Enable building a SPI ROM image on bob") Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-11-13video: rockchip: Restrict EDP, VOP, MIPI files to GPL-2.0Alper Nebi Yasak2-2/+2
These files have a lot of code in common with their counterparts in coreboot, especially in their earlier revisions: U-Boot | coreboot --------------------------------------|-------------------------------------------- drivers/video/rockchip/: | src/soc/rockchip/: - rk_edp.c (GPL-2.0+) | - common/edp.c (GPL-2.0-only) " | - rk3288/display.c (GPL-2.0-only) " | - rk3399/display.c (GPL-2.0-only) - rk_hdmi.h (GPL-2.0+) | (none) - rk_hdmi.c (GPL-2.0+) | - rk3288/hdmi.c (GPL-2.0-or-later) - rk3288_hdmi.c (GPL-2.0+) | - rk3288/hdmi.c (GPL-2.0-or-later) - rk3399_hdmi.c (GPL-2.0+) | (none) - rk_mipi.h (GPL-2.0+) | (none) - rk_mipi.c (GPL-2.0+) | - rk3399/mipi.c (GPL-2.0-only) - rk3288_mipi.c (GPL-2.0+) | - rk3399/mipi.c (GPL-2.0-only) - rk3399_mipi.c (GPL-2.0+) | - rk3399/mipi.c (GPL-2.0-only) - rk_lvds.c (GPL-2.0+) | (none) - rk_vop.h (GPL-2.0+) | (none) - rk_vop.c (GPL-2.0+) | - common/vop.c (GPL-2.0-only) - rk3288_vop.c (GPL-2.0+) | - common/vop.c (GPL-2.0-only) - rk3399_vop.c (GPL-2.0+) | (none) | arch/arm/include/asm/arch-rockchip/: | src/soc/rockchip/*/include/soc/*: - edp_rk3288.h (GPL-2.0+) | - common/.../edp.h (GPL-2.0-only) " | - rk3288/.../display.h (GPL-2.0-only) " | - rk3399/.../display.h (GPL-2.0-only) - vop_rk3288.h (GPL-2.0+) | - common/.../vop.h (GPL-2.0-only) Restrict the licenses to match coreboot's so that changes from coreboot can be imported to U-Boot as necessary. HDMI files are already 2.0+ there and rk_lvds.c has no counterpart, so keep them as is. Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Eric Gao <eric.gao@rock-chips.com> Cc: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-11-12ARM: dts: meson-sm1: add u-boot specific MMC controller compatibleNeil Armstrong6-4/+24
In order to enable the Amlogic SM1 MMC controller fix, we need to add a u-boot specific MMC controller compatible. This adds a new meson-sm1-u-boot.dtsi and reworks the other -u-boot.dtsi to use this for SM1 based boards. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-11-12mmc: meson-gx: move arch header to local headerNeil Armstrong1-92/+0
Move the asm/arch-meson/sd_emmc.h to a local meson_gx_mmc.h, remove the useless if/then and fix the meson_gx_mmc.c include. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-11-12ARM: mach-meson: update SoC IDsNeil Armstrong1-1/+6
Update From Linux commits - 240051cb833b ("soc: amlogic: meson-gx-socinfo: Add A1 and A113L IDs") - 1d7c541b8a5b ("soc: amlogic: meson-gx-socinfo: Add S905X3 ID for VIM3L") - fdfc6997bd08 ("soc: amlogic: meson-gx-socinfo: Fix S905D3 ID for VIM3L") - d16d0481e6ba ("soc: amlogic: meson-gx-socinfo: Fix S905X3 and S905D3 ID's") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-11-10x86: coral: Update smbios tables to latest definitionSimon Glass1-6/+21
The accepted binding uses multiple nodes, one for each table type. Update coral accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-10x86: Avoid using hardcoded number of variable range MTRRs in mtrr_commit()Bin Meng1-1/+1
Since commit 29d2d64ed55f ("x86: Add support for more than 8 MTRRs"), the maximum number of variable range MTRRs was increased from 8 to 10. On the BayTrail platform there are only 8 variable range MTRRs. In mtrr_commit() it still uses MTRR_MAX_COUNT which caused a #GP during VESA video driver probe. It should have been updated to use dynamically probed number. This fixes the boot failure seen on Intel Minnow Max board. Fixes: 29d2d64ed55f ("x86: Add support for more than 8 MTRRs") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-08-06 06:16:35 +0000