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2022-03-28video: fsl: colibri_vf: Drop FSL DCU driverSimon Glass2-5/+0
This does not use driver model and is more than two years past the migration date. Drop it. It can be added back later if needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-28video: Drop references to CONFIG_VIDEO et alSimon Glass2-10/+2
Drop the Kconfigs which are not used and all references to them. In particular, this drops CONFIG_VIDEO to avoid confusion and allow us to eventually rename CONFIG_DM_VIDEO to CONFIG_VIDEO. Also drop the prototype for video_get_info_str() which is no-longer used. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jason Liu <jason.hui.liu@nxp.com>
2022-03-28video: Drop video_fb headerSimon Glass1-1/+0
This is not used now. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-28video: nexell: Drop unused and invalid codeSimon Glass1-2/+2
Unfortunately this driver uses the old video structure to store things. This is not supported with driver model. Drop the old code and comment out the other pieces, so the maintainer can take a look. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-28Merge tag 'v2022.04-rc5' into nextTom Rini37-151/+971
Prepare v2022.04-rc5
2022-03-28arm: apple: Fix mem layoutMark Kettenis1-18/+14
The current approach for setting the environment variables that describe the memory layout runs the risk of overlapping with reserved memory regions. Use the lmb code to derive the addresses for these variables instead. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-03-28arm: apple: Increase RTKit timeoutHector Martin1-1/+1
The firmware on larger NVMe drives needs more than 100ms to come up. Change the timeout to 1s. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-03-26sunxi: dts: Update RGMII phy-mode propertiesAndre Przywara14-14/+14
Commit f11513d99787 ("net: phy: realtek: Add tx/rx delay config for 8211e") made the Realtek PHY driver honour the phy-mode DT property, to set up the proper delay scheme for the RX and TX lines. A similar change in the kernel revealed that those properties were mostly wrong. The kernel DTs got updated over the last few months, but we were missing out on the U-Boot version. Just sync in the phy-mode properties from the mainline kernel, v5.17-rc7, to avoid the breaking DT sync that late in the cycle. This fixes Ethernet operation on the affected boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-03-26sunxi: Fix old GMAC pinmux setupAndre Przywara1-1/+0
Commit 5bc4cd05d7d4 ("sunxi: move non-essential code out of s_init()") moved the call to eth_init_board() from s_init() into board_init_f(). This means it's now only called from the SPL, which makes sense for most of the other moved low-level functions. However the GMAC pinmux and clock setup in eth_init_board() was not happy about that, so it broke the sun7i GMAC. Since Ethernet is of no use in the SPL anyway, just move the call into board_init(), which is only run in U-Boot proper. This fixes Ethernet operation for the A20 SoCs, which broke in v2022.04-rc1, with the above mentioned commit. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by: Petr Štetiar <ynezz@true.cz> [a20-olinuxino-lime2]
2022-03-25ARM: dts: ast2600: Add PWM to device treeBilly Tsai2-0/+35
Add the PWM node and enable it for AST2600 EVB Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2022-03-25pinctrl: Add the pinctrl setting for PWM.Billy Tsai1-0/+80
This patchs add the signal description array for PWM pinctrl settings. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2022-03-25sandbox: video: Replace PCI_CLASS_* macros by one from pci_ids.hPali Rohár1-2/+3
Replace old macros PCI_CLASS_CODE_COMM and PCI_CLASS_SUB_CODE_COMM_SERIAL by new macros defined in pci_ids.h. Old macros would be deleted in followup commit. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-03-25Split CONFIG_CC_OPTIMIZE_FOR_SIZE into two configsSean Anderson1-1/+1
This adds a separate CONFIG_CC_OPTIMIZE_FOR_SPEED option in a choice, in preparation for adding another optimization option. Also convert SH's makefile to use this new option. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-03-25Convert CONFIG_BACKSIDE_L2_CACHE to KconfigTom Rini1-0/+10
This converts the following to Kconfig: CONFIG_BACKSIDE_L2_CACHE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-25Convert CONFIG_PHY_RESET_DELAY to KconfigTom Rini1-3/+0
This converts the following to Kconfig: CONFIG_PHY_RESET_DELAY Cc: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-25Convert CONFIG_SYS_FAULT_ECHO_LINK_DOWN to KconfigTom Rini1-7/+0
This converts the following to Kconfig: CONFIG_SYS_FAULT_ECHO_LINK_DOWN Cc: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-25Convert CONFIG_RESET_PHY_R to KconfigTom Rini1-1/+0
This converts the following to Kconfig: CONFIG_RESET_PHY_R Cc: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-25Convert CONFIG_AT91_WANTS_COMMON_PHY to KconfigTom Rini1-0/+9
This converts the following to Kconfig: CONFIG_AT91_WANTS_COMMON_PHY Cc: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-24arm: a37xx: espressobin: Fix non-working SPIPali Rohár1-3/+10
Commit 0934dddc6436 ("arm: a37xx: Update DTS files to version from upstream Linux kernel") ported Linux's device-tree files for Armada 3720 SOCs. This broke SPI support on some Espressobin boards and results in following U-Boot error: Loading Environment from SPIFlash... jedec_spi_nor flash@0: unrecognized JEDEC id bytes: f7, 30, 0b *** Warning - spi_flash_probe_bus_cs() failed, using default environment Before that commit DT node for SPI was called 'spi-flash@0' and after that commit it is called 'flash@0'. Before that commit 'spi-max-frequency' was set to 50000000 and after it is 104000000. Rename DT node 'spi-flash@0 in armada-3720-espressobin-u-boot.dtsi to 'flash@0' and set custom U-Boot 'spi-max-frequency' back to 50000000. With this change SPI is working on Espressobin again and it is detected with JEDEC ids ef, 60, 16 on our tested unit. Loading Environment from SPIFlash... SF: Detected w25q32dw with page size 256 Bytes, erase size 4 KiB, total 4 MiB OK Note that it is unknown why spi-max-frequency with value 104000000 does not work in U-Boot as it works fine with Linux kernel. Also note that in defconfig file configs/mvebu_espressobin-88f3720_defconfig is set option CONFIG_SF_DEFAULT_SPEED=40000000 which is different value than in DT. Fixes: 0934dddc6436 ("arm: a37xx: Update DTS files to version from upstream Linux kernel") Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-03-23arm: mvebu: dts: turris_mox: fix non-working USB portMarek Behún1-0/+4
Commit 0934dddc6436 ("arm: a37xx: Update DTS files to version from upstream Linux kernel") ported Linux's device-tree files for Armada 3720 SOCs. This broke USB port on Turris MOX, because in Linux' DTS the bus voltage supply is described as a `phy-supply` property of connector node, a mechanism that is not supported in U-Boot yet. For now, fix this by adding `vbus-supply` to usb3 node. Fixes: 0934dddc6436 ("arm: a37xx: Update DTS files to version from upstream Linux kernel") Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2022-03-19Merge tag 'dm-pull-18mar22' of ↵WIP/19Mar2022-nextTom Rini2-1/+3
https://source.denx.de/u-boot/custodians/u-boot-dm into next binman FIT improvements various minor sandbox improvements
2022-03-18sandbox: Add the handoff header for splSimon Glass1-0/+1
This defines a function declared in handoff.h so add the header. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-18sandbox: Show a message when writing out the ram bufferSimon Glass1-1/+2
If state is not being written, but RAM is, we should still show a message, so it is clear that this is happening. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-18Convert CONFIG_ATMEL_LEGACY to KconfigTom Rini1-0/+3
This converts the following to Kconfig: CONFIG_ATMEL_LEGACY Cc: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18Convert CONFIG_AT91_GPIO_PULLUP to KconfigTom Rini1-0/+4
This converts the following to Kconfig: CONFIG_AT91_GPIO_PULLUP Cc: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18Convert CONFIG_AT91SAM9260 et al to KconfigTom Rini1-0/+1
This converts the following to Kconfig: CONFIG_AT91SAM9260 CONFIG_AT91SAM9G20 CONFIG_AT91SAM9XE CONFIG_AT91SAM9261 CONFIG_AT91SAM9263 CONFIG_AT91SAM9G45 CONFIG_AT91SAM9M10G45 CONFIG_AT91SAM9N12 CONFIG_AT91SAM9RL CONFIG_AT91SAM9X5 CONFIG_SAM9X60 CONFIG_SAMA7G5 CONFIG_SAMA5D2 CONFIG_SAMA5D3 CONFIG_SAMA5D4 These options are already select'd as needed, so we're just cleaning up files here. Cc: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18Convert CONFIG_AM335X_USB0 et al to KconfigTom Rini2-4/+36
This converts the following to Kconfig: CONFIG_AM335X_USB0 CONFIG_AM335X_USB0_MODE CONFIG_AM335X_USB1 CONFIG_AM335X_USB1_MODE We do this by introducing specific options for static configuration of USB0/USB1 in SPL rather than defining CONFIG_AM335X_USBx_MODE to the enum value being used. Furthermore, with how the code is used now we do not need to have OTG mode exposed as an option here, so remove that. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18Remove CONFIG_HAS_ETH0 et al symbolsTom Rini1-8/+0
This converts removes the following symbols: CONFIG_HAS_ETH0 CONFIG_HAS_ETH1 CONFIG_HAS_ETH2 CONFIG_HAS_ETH3 This is because at this point, only the ids8313 platform was using the code which was controlled by these symbols. In turn, this code already performs error checking on being able to perform the device tree fixup. Rather than convert these to Kconfig for a single platform, update the code to not need these checks and remove them from all the platforms they were unused on. Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18powerpc: Move CONFIG_BPTR_VIRT_ADDR out of CONFIG namespaceTom Rini2-6/+4
This is only used in one file, and is never overridden. Move this out of CONFIG namespace. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18Convert CONFIG_NET_RETRY_COUNT to KconfigTom Rini1-7/+0
This converts the following to Kconfig: CONFIG_NET_RETRY_COUNT Cc: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18Convert CONFIG_ARP_TIMEOUT to KconfigTom Rini1-1/+0
This converts the following to Kconfig: CONFIG_ARP_TIMEOUT Cc: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18Convert CONFIG_A008044_WORKAROUND to KconfigTom Rini1-0/+7
This converts the following to Kconfig: CONFIG_A008044_WORKAROUND Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18Convert CONFIG_A003399_NOR_WORKAROUND to KconfigTom Rini1-0/+7
This converts the following to Kconfig: CONFIG_A003399_NOR_WORKAROUND Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18Convert CONFIG_ARMV8_SWITCH_TO_EL1 to KconfigTom Rini1-0/+6
This converts the following to Kconfig: CONFIG_ARMV8_SWITCH_TO_EL1 Cc: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com>
2022-03-18Convert CONFIG_ARMV7_SECURE_BASE et al to KconfigTom Rini1-0/+31
This converts the following to Kconfig: CONFIG_ARMV7_SECURE_BASE CONFIG_ARMV7_SECURE_MAX_SIZE CONFIG_ARMV7_SECURE_RESERVE_SIZE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18rockchip: Set default LNX_KRNL_IMG_TEXT_OFFSET_BASE to SYS_TEXT_BASEAlper Nebi Yasak1-0/+3
U-Boot can be chainloaded from vendor firmware on ARM64 chromebooks from a GPT partition (roughly the same as in doc/chromium/chainload.rst), but an appropriate image header must be built-in to the U-Boot binary by enabling LINUX_KERNEL_IMAGE_HEADER. This header has a field for an image load offset from 2MiB alignment which must also be customized through LNX_KRNL_IMG_TEXT_OFFSET_BASE. Set it equal to SYS_TEXT_BASE by default for Rockchip boards, which happens to make this offset zero and works fine on chromebook_kevin both for chainloading and bare-metal use. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-03-18rockchip: rk3399: Add support for chromebook_kevinMarty E. Plummer5-2/+27
Add support for Kevin, an RK3399-based convertible chromebook that is very similar to Bob. This patch is mostly based on existing support for Bob, with only minor changes for Kevin-specific things. Unlike other Gru boards, coreboot sets Kevin's center logic to 925 mV, so adjust it here in the dts as well. The rk3399-gru-kevin devicetree has an unknown event code reference which has to be defined, set it to the Linux counterpart. The new defconfig is copied from Bob with the diffconfig: DEFAULT_DEVICE_TREE "rk3399-gru-bob" -> "rk3399-gru-kevin" DEFAULT_FDT_FILE "rockchip/rk3399-gru-bob.dtb" -> "rockchip/rk3399-gru-kevin.dtb" VIDEO_ROCKCHIP_MAX_XRES 1280 -> 2400 VIDEO_ROCKCHIP_MAX_YRES 800 -> 1600 +TARGET_CHROMEBOOK_KEVIN y With this Kevin can boot from SPI flash to a usable U-Boot prompt on the display with the keyboard working, but cannot boot into Linux for unknown reasons. eMMC starts in a working state but fails to re-init, microSD card works but at a lower-than-expected speed, USB works but causes a hang on de-init. There are known workarounds to solve eMMC and USB issues. Cc: Marty E. Plummer <hanetzer@startmail.com> Cc: Simon Glass <sjg@chromium.org> [Alper: commit message, resync config with Bob, update MAINTAINERS, add to Rockchip doc, add Kconfig help message, set regulator] Co-developed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2022-03-18rockchip: gru: Add more devicetree settingsSimon Glass1-0/+55
This adds some devicetree settings for the Gru-based boards, based on what works on a Kevin board. Gru-based boards usually have an 8MiB SPI flash chip and boot from it. Make the u-boot.rom file intended to be flashed on it match its size. Add properties for booting from SPI, and only try to boot from SPI as MMC and SD card don't seem to work in SPL yet. The Chromium OS EC needs a delay between transactions so it can get itself ready. Also it currently uses a non-standard way of specifying the interrupt. Add these so that the EC works reliably. The Rockchip Embedded DisplayPort driver is looking for a rockchip,panel property to find the panel it should work on. Add the property for the Gru-based boards. The U-Boot GPIO controlled regulator driver only considers the "enable-gpios" devicetree property, not the singular "enable-gpio" one. Some devicetree source files have the singular form as they were added to Linux kernel when it used that form, and imported to U-Boot as is. Fix one instance of this in the Gru boards' devicetree to the form that works in U-Boot. The PWM controlled regulator driver complains that there is no init voltage set for a regulator it drives, though it's not clear which one. Set them all to the voltage levels coreboot sets them: 900 mV. The RK3399 SoC needs to know the voltage level that some supplies provides, including one fixed 1.8V audio-related regulator. Although this synchronization is currently statically done in the board init functions, a not-so-hypothetical driver that does this dynamically would query the regulator only to get -ENODATA and be confused. Make sure U-Boot knows this supply is at 1.8V by setting its limits to that. Most of this is a reapplication of commit 08c85b57a5ec ("rockchip: gru: Add extra device-tree settings") whose changes were removed during a sync with Linux at commit 167efc2c7a46 ("arm64: dts: rk3399: Sync v5.7-rc1 from Linux"). Apply things to rk3399-gru-u-boot.dtsi instead so they don't get lost again. Signed-off-by: Simon Glass <sjg@chromium.org> [Alper: move to -u-boot.dtsi, rewrite commit message, add more nodes] Co-developed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2022-03-16Merge tag 'xilinx-for-v2022.07-rc1' of ↵WIP/16Mar2022-nextTom Rini11-44/+115
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.07-rc1 microblaze: - Add support for reserved memory xilinx: - Update FRU code with MAC reading zynqmp: - Remove double AMS setting - DT updates (mostly for SOMs) - Add support for zcu106 rev 1.0 zynq: - Update nand binding nand: - Aligned zynq_nand to upstream DT binding net: - Add support for ethernet-phy-id mmc: - Workaround CD in zynq_sdhci driver also for ZynqMP - Add support for dynamic/run-time SD config for SOMs gpio: - Add driver for slg7xl45106 firmware: - Add support for dynamic SD config power-domain: - Update zynqmp driver with the latest firmware video: - Add skeleton driver for DP and DPDMA i2c: - Fix i2c to work with QEMU pinctrl: - Add driver for zynqmp pinctrl driver
2022-03-16arm64: zynqmp: Add pinctrl emmc description to SM-K26Michal Simek1-0/+20
Production SOM has emmc on it and make sense to describe pin description to be able use EMMC if it is not configured via psu_init. (Still some regs are not handled but this is one step in that direction) Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/3545a0f08d342de98efc82b78f5725eda091555a.1647267969.git.michal.simek@xilinx.com
2022-03-16Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini1-0/+23
- mvebu: dts: turris_mox: fix non-working network / MDIO (Marek)
2022-03-16Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini2-75/+105
- k210 updates
2022-03-16arm: mvebu: dts: turris_mox: fix non-working network / MDIOMarek Behún1-0/+23
Commit 0934dddc6436 ("arm: a37xx: Update DTS files to version from upstream Linux kernel") ported Linux's device-tree files for Armada 3720 SOCs. This broke network on Turris MOX, because the SOC's MDIO bus in U-Boot currently isn't probed via DM as it's own device, but is registered as part of mvneta's driver, which means that pinctrl definitions are not parsed for the MDIO bus node. Also mvneta driver does not consider "phy-handle" property, only "phy". For now, fix this by adding armada-3720-turris-mox-u-boot.dtsi file returning the MDIO to how it was defined previously. A better solution (using proper mvmdio DM driver) is being work on, but will need testing on various boards, and we need the bug fixed now for the upcoming release. Fixes: 0934dddc6436 ("arm: a37xx: Update DTS files to version from upstream Linux kernel") Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2022-03-15k210: dts: align plic node with LinuxNiklas Cassel1-2/+2
The Linux PLIC interrupt-controller driver actually initializes the hart context registers in the PLIC driver exactly in the same order as specified in the interrupts-extended device tree property. See the device tree binding [1]. The ordering of the interrupts is therefore essential in order to configure the PLIC correctly. Fix the order so that we will have sane IRQ behavior when booting Linux with the u-boot device tree. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-03-15k210: dts: align fpioa node with LinuxDamien Le Moal1-2/+1
Linux kernel fpioa pinctrl driver expects the sysctl phandle and the power bit offset of the fpioa device to be specified as a single property "canaan,k210-sysctl-power". Replace the "canaan,k210-sysctl" and "canaan,k210-power-offset" properties with "canaan,k210-sysctl-power" to satisfy the Linux kernel requirements. This new property is parsed using the existing function dev_read_phandle_with_args(). Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-03-15k210: dts: add missing power bus clocksDamien Le Moal1-23/+53
Linux drivers for many of the K210 peripherals depend on the power bus clock to be specified. Add the missing clocks and their names to avoid problems when booting Linux using u-boot DT. Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-03-15k210: use the board vendor name rather than the marketing nameDamien Le Moal2-50/+51
"kendryte" is the marketing name for the K210 RISC-V SoC produced by Canaan Inc. Rather than "kendryte,k210", use the usual "canaan,k210" vendor,SoC compatibility string format in the device tree files and use the SoC name for file names. With these changes, the device tree files are more in sync with the Linux kernel DTS and drivers, making uboot device tree usable by the kernel. Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-03-15ARM: dts: stm32: Add DFU support for DHCOM recoveryMarek Vasut1-0/+42
This patch configures U-Boot SPL for DHCOM SoM to permit DFU upload of SPL and subsequent u-boot.itb for recovery or commissioning purposes. The DFU usage procedure is identical to STM32MP1 DHCOR SoM, see commit 3919aa1722a ("ARM: dts: stm32: Add DFU support for DHCOR recovery") , except for switching the SoM into DFU mode. By default, the DHCOM SoM has no dedicated mechanism for setting BOOTn straps into UART/USB mode, therefore to enter DFU mode, the SoC must fail to boot from boot media which can be selected by the BOOTn strap override mechanism first and then fall back to DFU mode. In case of a SoM with pre-populated BOOTn strap override button, power the system off, remove microSD card (if applicable), hold down the BOOTn strap override button located between eMMC and SoM edge connector, power on the SoM. The SoC will fail to boot from SD card and fall back into DFU mode. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-03-15stm32mp: psci: Implement PSCI system suspend and DRAM SSRMarek Vasut2-11/+519
Implement PSCI system suspend and placement of DRAM into SSR while the CPUs are in suspend. This saves non-trivial amount of power in suspend, on 2x W632GU6NB-15 ~710mW. Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com>
2022-03-15ARM: dts: stm32: Move vdd_io extras into Avenger96 extrasMarek Vasut2-4/+4
The vdd_io regulator is present only on DHCOR SoM configured for 1V8 IO, as populated on Avenger96, but not present on 3V3 DHCOR SoM. Move these extras to Avenger96 u-boot DT extras. Fixes: 3919aa1722a ("ARM: dts: stm32: Add DFU support for DHCOR recovery") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>