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2021-04-27Merge branch '2021-04-27-assorted-fixes'Tom Rini2-9/+7
- An assortment of bug fixes
2021-04-27test: reset: Extend base reset test to catch errorNeil Armstrong1-2/+2
With this extended test, we get the following failure : => ut dm reset_base Test: dm_test_reset_base: reset.c test/dm/reset.c:52, dm_test_reset_base(): reset_method3.id == reset_method3_1.id: Expected 0x14 (20), got 0x2 (2) Test: dm_test_reset_base: reset.c (flat tree) test/dm/reset.c:52, dm_test_reset_base(): reset_method3.id == reset_method3_1.id: Expected 0x14 (20), got 0x2 (2) Failures: 2 A fix is needed in reset_get_by_index_nodev() when introduced in [1]. [1] ea9dc35aab ("reset: Get the RESET by index without device") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-27arm: zimage: Use correct symbol to hide messages in SPLSamuel Holland1-7/+5
When zImage support was added to SPL, the messages were hidden to reduce code size. However, the wrong config symbol was used. Since this file is only built when CONFIG_SPL_FRAMEWORK=y, the messages were always hidden. Use the correct symbol so the messages are printed in U-Boot proper. Also use IS_ENABLED to drop the #ifdef. Fixes: 431889d6ad9a ("spl: zImage support in Falcon mode") Signed-off-by: Samuel Holland <samuel@sholland.org>
2021-04-27powerpc: introduce CONFIG_CACHE_FLUSH_WATCHDOG_THRESHOLDRasmus Villemoes3-2/+23
When flush_cache() is called during boot on our ~7M kernel image, the hundreds of thousands of WATCHDOG_RESET calls end up adding significantly to boottime. Flushing a single cache line doesn't take many microseconds, so doing these calls for every cache line is complete overkill. The generic watchdog_reset() provided by wdt-uclass.c actually contains some rate-limiting logic that should in theory mitigate this, but alas, that rate-limiting must be disabled on powerpc because of its get_timer() implementation - get_timer() works just fine until interrupts are disabled, but it just so happens that the "big" flush_cache() call happens in the part of bootm where interrupts are indeed disabled. [1] [2] [3] I have checked with objdump that the generated code doesn't change when this option is left at its default value of 0: gcc is smart enough to see that the ">=" comparison is tautologically true, hence all assignments to "flushed" are eliminated as dead stores. On our board, setting the option to something like 65536 ends up reducing total boottime by about 0.8 seconds. [1] https://patchwork.ozlabs.org/project/uboot/patch/20200605111657.28773-1-rasmus.villemoes@prevas.dk/ [2] https://lists.denx.de/pipermail/u-boot/2021-April/446906.html [3] https://lists.denx.de/pipermail/u-boot/2021-April/447280.html Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-04-27powerpc: lib: remove leftover CONFIG_5xxRasmus Villemoes1-2/+0
CONFIG_5xx hasn't existed since commit 502589777416 (powerpc, 5xx: remove support for 5xx). Remove this last mention of it. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-04-27allow opting out of WATCHDOG_RESET() from timer interruptRasmus Villemoes2-2/+2
Having WATCHDOG_RESET() called automatically from the timer interrupt runs counter to the idea of a watchdog device - if the board runs into an infinite loops with interrupts still enabled, the watchdog will never fire. When using CONFIG_(SPL_)WDT, the watchdog_reset function is a lot more complicated than just poking a few SOC-specific registers - it involves accessing all kinds of global data, and if the interrupt happens at the wrong time (say, in the middle of an WATCHDOG_RESET() call from ordinary code), that can end up corrupting said global data. Allow the board to opt out of calling WATCHDOG_RESET() from the timer interrupt handler by setting CONFIG_SYS_WATCHDOG_FREQ to 0 - as that setting is currently nonsensical (it would be compile-time divide-by-zero), it cannot affect any existing boards. Add documentation for both the existing and extended meaning of CONFIG_SYS_WATCHDOG_FREQ. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-04-26sunxi: DT: A64: Update devicetree files from Linux 5.12Andre Przywara17-76/+215
Import updated devicetree files from the Linux v5.12 release. Besides some node and audio port renames this changes the PHY modes to either rgmii-id or rgmii-txid. From the board files the Pinephone sees a lot of updates. This also adds the long missing USB PHY property for controller 0, which allows the U-Boot PHY driver to eventually use port 0 in host mode (pending another U-Boot patch). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
2021-04-26sunxi: DT: R40: Update device tree files from Linux 5.12Ivan Uvarov3-44/+366
Update R40 .dts{,i} and dt-binding headers to current version from kernel. Files taken from Linux 5.12-rc1 release (commit fe07bfda2fb9cdef8a4d4008a409bb02f35f1bd8) Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-04-24Merge tag 'mips-pull-2021-04-24' of ↵WIP/24Apr2021Tom Rini109-220/+118943
https://source.denx.de/u-boot/custodians/u-boot-mips - MIPS: octeon: fix minor bugs of initial merge - MIPS: octeon: add support for QLM and PCI-E controller - MIPS: octeon: add support for AHCI and SATA - MIPS: octeon: add E1000 ethernet support - MIPS: octeon: add Octeon III NIC23 board - ata/scsi: add support for Big Endian platforms
2021-04-23mips: octeon: ebb7304: Add support for some I2C devicesAaron Williams1-0/+11
This patch adds support for the following I2C devices connected to I2C bus 0 on the Octeon EBB7304: - Dallas DS1337 RTC - TLV EEPROM Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-23mips: octeon: dts/dtsi: Change UART DT node to use clocks propertyAaron Williams2-4/+2
We already have a clock driver for MIPS Octeon. This patch changes the Octeon DT nodes to supply the clock property via the clock driver instead of using an hard-coded value, which is not correct in all cases. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-23mips: octeon: Add Octeon III NIC23 board supportStefan Roese3-0/+170
This patch adds the basic support for the PCIe target board equipped with the Octeon III CN2350 SoC. Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: mrvl, cn73xx.dtsi: Add AHCI/SATA DT nodeStefan Roese1-0/+19
Add the AHCI compatible SATA DT node to the Octeon CN73xx dtsi file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-23mips: octeon: cpu.c: Enable AHCI/SATA supportStefan Roese1-1/+20
For easy AHCI/ SATA integration, this patch adds board_ahci_enable() for the MVEBU AHCI driver, which will be used by this platform. This platform specific "enable" function will setup the proper endian swapping in the AHCI controller so that it can be used by the common AHCI code. Additionally the endian swizzle entry for AHCI in octeon_should_swizzle_table[] is removed, as this enabled the original lowlevel code function, e.g. octeon_configure_qlm(), for the QLM setup to work correctly. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-23mips: octeon: cpu.c: Add arch_misc_init() for pci-console & pci-bootcmdStefan Roese1-0/+327
This patch adds the necessary platform infrastructure code, so that the MIPS Octeon drivers "serial_octeon_pcie_console" & "serial_bootcmd" can be used. This is e.g. the bootmem initialization in a compatible way to the Marvell 2013 U-Boot, so that the exisiting PC remote tools like "oct-remote-console" & "oct-remote-load" can be used. This is be done in the newly introduced arch_misc_init(), which calls the necessary init functions when enabled. These patches are in preparation for the MIPS Octeon NIC23 board support, which is a desktop PCIe target board enabling these features. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-23mips: octeon: cvmx-coremask.h: Fix cvmx_coremask_dprint() with DEBUG definedStefan Roese1-2/+3
As DEBUG is no Kconfig symbol, we can't use the IS_ENABLED() macros. This patch switches to the unfortunately necessary #ifdef usage again to make it work correctly. Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: cvmx-bootmem: Fix compare in "if" statementStefan Roese1-2/+2
While porting from the Marvell source, I introduced a bug by misplacing the parenthesis. This patch fixes this issue. Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Move CVMX_SYNC from octeon_ddr.h to cvmx-regs.hStefan Roese2-2/+1
This makes is easier to use this macro from non-DDR related files. Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: mrvl, cn73xx.dtsi: Add PCIe controller DT nodeStefan Roese1-0/+16
This patch adds the PCIe controller node to the MIPS Octeon 73xx dtsi file. Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Kconfig: Enable CONFIG_SYS_PCI_64BITStefan Roese1-0/+4
Setting CONFIG_SYS_PCI_64BIT is needed for correct PCIe functionality on MIPS Octeon. Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Makefile: Enable building of the newly added C filesStefan Roese1-0/+11
This patch adds the newly added C files to the Makefile to enable compilation. This is done in a separate step, to not introduce build breakage while adding the single files with potentially missing externals. Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add octeon_qlm.cAaron Williams1-0/+5853
Import octeon_qlm.c from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add octeon_fdt.cAaron Williams1-0/+1040
Import octeon_fdt.c from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-qlm.cAaron Williams1-0/+2350
Import cvmx-qlm.c from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-pcie.cAaron Williams1-0/+2487
Import cvmx-pcie.c from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-helper.cAaron Williams1-0/+2611
Import cvmx-helper.c from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-helper-util.cAaron Williams1-0/+1225
Import cvmx-helper-util.c from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-helper-jtag.cAaron Williams1-0/+172
Import cvmx-helper-jtag.c from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-helper-fdt.cAaron Williams1-0/+970
Import cvmx-helper-fdt.c from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-helper-cfg.cAaron Williams1-0/+1914
Import cvmx-helper-cfg.c from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Move cvmx-lmcx-defs.h from mach/cvmx to machStefan Roese2-1/+1
To match all other cvmx-* header, this patch moves the already existing cvmx-lmcx-defs.h header one directory up. Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Misc changes required because of the newly added headersStefan Roese7-208/+321
With the newly added headers and their restructuring (which macro is defined where), some changes in the already existing Octeon files are necessary. This patch makes the necessary changes. Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add misc remaining header filesAaron Williams29-0/+12242
Import misc remaining header files from 2013 U-Boot. These will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-23mips: octeon: Add cvmx-sso-defs.h header fileAaron Williams1-0/+2904
Import cvmx-sso-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-sriox-defs.h header fileAaron Williams1-0/+44
Import cvmx-sriox-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-sriomaintx-defs.h header fileAaron Williams1-0/+61
Import cvmx-sriomaintx-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-smix-defs.h header fileAaron Williams1-0/+360
Import cvmx-smix-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-sli-defs.h header fileAaron Williams1-0/+6548
Import cvmx-sli-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-sata-defs.h header fileAaron Williams1-0/+311
Import cvmx-sata-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-rst-defs.h header fileAaron Williams1-0/+77
Import cvmx-rst-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-pow-defs.h header fileAaron Williams1-0/+1135
Import cvmx-pow-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-pko-defs.h header fileAaron Williams1-0/+9388
Import cvmx-pko-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-pki-defs.h header fileAaron Williams1-0/+2353
Import cvmx-pki-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-pip-defs.h header fileAaron Williams1-0/+3040
Import cvmx-pip-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-pepx-defs.h header fileAaron Williams1-0/+1382
Import cvmx-pepx-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-pemx-defs.h header fileAaron Williams1-0/+2028
Import cvmx-pemx-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-pcsx-defs.h header fileAaron Williams1-0/+1005
Import cvmx-pcsx-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-pciercx-defs.h header fileAaron Williams1-0/+5586
Import cvmx-pciercx-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-pcieepx-defs.h header fileAaron Williams1-0/+6848
Import cvmx-pcieepx-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23mips: octeon: Add cvmx-npi-defs.h header fileAaron Williams1-0/+1953
Import cvmx-npi-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
generated by cgit v1.1 at 2024-10-17 16:13:46 +0000