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2022-06-23sandbox: Rename getopt sectionsAndrew Scull4-9/+9
Rename the sections used for defining sandbox command line options so that they don't start with a '.'. ELF says that sections starting with a '.' are reserved for system use, but the sandbox runs as a normal user process so should be using user sections instead. Clang's ASAN adds redzones to non-user sections and the extra padding meant that the list of options was being corrupted. Naming the sections as user sections avoids this issue as clang handles them as we intended. Signed-off-by: Andrew Scull <ascull@google.com>
2022-06-23sandbox: Rename EFI runtime sectionsAndrew Scull2-16/+14
Rename the sections used for placing the EFI runtime so that they don't start with a '.'. ELF says that sections starting with a '.' are reserved for system use, but the sandbox runs as a normal user process so should be using user sections instead. Clang's ASAN adds redzones to non-user sections and the extra padding meant that the list of options was being corrupted. Naming the sections as user sections avoids this issue as clang handles them as we intended. Signed-off-by: Andrew Scull <ascull@google.com>
2022-06-22misc: nuvoton: Add NPCM7xx otp controller driverJim Liu1-0/+90
Add Nuvoton BMC npcm750 otp driver Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-22crypto: nuvoton: Add NPCM7xx AES driverJim Liu1-0/+53
add nuvoton BMC npcm750 AES driver Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-22ast2600: spl: Add boot mode detectionChia-Wei Wang2-0/+33
AST2600 supports boot from SPI(mmap), eMMC, and UART. This patch adds the boot mode detection and return the corresponding boot device type. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2022-06-22configs: ast2600: Move SPL bss section to DRAM spaceChia-Wei Wang1-0/+94
The commit b583348ca8c8 ("image: fit: Align hash output buffers") places the hash output buffer at the .bss section. However, AST2600 by default executes SPL in the NOR flash XIP way. This results in the hash output cannot be written to the buffer as it is located at the R/X only region. We need to move the .bss section out of the SPL body to the DRAM space, where hash output can be written to. This patch includes: - Define the .bss section base and size - A new SPL linker script is added with a separate .bss region specified - Enable CONFIG_SPL_SEPARATE_BSS kconfig option Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Neal Liu <neal_liu@aspeedtech.com>
2022-06-22ARM: dts: Add device tree files for hpe gxp socNick Hawkins4-0/+180
The HPE SoC is new to linux. A basic device tree layout with minimum required for linux to boot including a timer and watchdog support has been created. The dts file is empty at this point but will be updated in subsequent updates as board specific features are enabled. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
2022-06-22ARM: hpe: gxp: add core supportNick Hawkins6-0/+45
The GXP is the HPE BMC SoC that is used in the majority of current generation HPE servers. Traditionally the asic will last multiple generations of server before being replaced. Info about SoC: HPE GXP is the name of the HPE Soc. This SoC is used to implement many BMC features at HPE. It supports ARMv7 architecture based on the Cortex A9 core. It is capable of using an AXI bus to whicha memory controller is attached. It has multiple SPI interfaces to connect boot flash and BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It has multiple i2c engines to drive connectivity with a host infrastructure. There currently are no public specifications but this process is being worked. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
2022-06-22arm: add support to corstone1000 platformRui Miguel Silva5-1/+257
Corstone1000 is a platform from arm, which includes pre verified Corstone SSE710 sub-system that combines Cortex-A and Cortex-M processors [0]. This code adds the support for the Cortex-A35 implementation at host side, it contains also the necessary bits to support the Corstone 1000 FVP (Fixed Virtual Platform) [1] and also the FPGA MPS3 board implementation of this platform. [2] 0: https://developer.arm.com/documentation/102360/0000 1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps 2: https://developer.arm.com/documentation/dai0550/c/ Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2022-06-22ARM: dts: omap3-devkit8000: Fix CONFIG_DM_ETH warningAnthoine Bourgeois1-0/+6
Add the missing ethernet node in u-boot dts. Signed-off-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
2022-06-22ARM: dts: omap3-devkit8000: Fix CONFIG_DM_I2C warningAnthoine Bourgeois1-0/+1
Seems that u-boot can't probe i2c bus at 2.6Mhz speed, so lower the speed to the default value 100Khz. v2: fix i2c1 frequency in the root omap3-u-boot.dtsi include. Signed-off-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
2022-06-22ARM: dts: omap3-devkit8000: Add support for Devkit8000Anthoine Bourgeois3-0/+365
This commit adds OMAP3 BeagleBoard devicetree files from Linux v5.16.0. This commit fixes CONFIG_DM_MMC warning. v3: patch clean-up Signed-off-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
2022-06-20Merge branch 'master' into nextTom Rini20-24/+741
Merge in v2022.07-rc5.
2022-06-20Merge tag 'u-boot-stm32-20220620' of ↵Tom Rini25-536/+1792
https://source.denx.de/u-boot/custodians/u-boot-stm into next - Add STM32MP13 SoCs support with associated board STM32M135F-DK - Correct livetree support in stm32mp1 boards - Activate livetree for stm32mp15 DHSOM boards
2022-06-20armv8: layerscape: add missing RCW source definesMichael Walle1-0/+4
A board might need to get the source of the RCW word, which is also the boot source in most cases. These defines are taken from the LS1028A and I expect they are the same across the SoCs with the same chassis, after all, there was already a reset source for NOR flash. Signed-off-by: Michael Walle <michael@walle.cc>
2022-06-20powerpc: bootm: Fix sizes in memory adjusting warningPali Rohár1-1/+2
Old size is stored in size variable and new size is in bootm_size variable. Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-20powerpc: dts: p2020: Define PMC nodePali Rohár1-0/+5
Copy definition of PMC node from upstream Linux kernel P2020 dts files. Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-20powerpc: mpc85xx: Set default SYS_IMMR value for P1/P2 CPUsPali Rohár1-0/+3
This reduce usage of per-board custom settings. Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-20powerpc: mmu: Fix FSL_BOOKE_MAS2() macroPali Rohár1-1/+1
Effective page number mask for MAS2 register is stored in macro MAS2_EPN. Fixes: 2146cf56821c ("Reworked FSL Book-E TLB macros to be more readable") Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-20powerpc: fsl_law: Add definition for first PCIe target interfacePali Rohár1-0/+1
Header file asm/fsl_law.h already provides correct definition for second and third PCIe controller (LAW_TRGT_IF_PCIE_2 and LAW_TRGT_IF_PCIE_3). But is missing definition for the first PCIe controller (LAW_TRGT_IF_PCIE_1). Note that existing definition for LAW_TRGT_IF_PCIE_2 and LAW_TRGT_IF_PCIE_3 are slightly complicated, but are really correct for P2020 platform. Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-20powerpc: mpc85xx: Fix compilation with CONFIG_WDTPali Rohár1-0/+2
When CONFIG_WDT is enabled then non-DM watchdog code cannot be used due to conflicting functions like watchdog_reset(). So disable compilation of mpc85xx watchdog_reset() function when CONFIG_WDT is enabled. Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-20powerpc: dts: p2020: Define ecm, memory and guts nodesPali Rohár1-0/+24
Copy definition of these nodes from upstream Linux kernel P2020 dts files. Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-20powerpc: dts: p2020: Define DMA nodesPali Rohár3-0/+135
Copy definition of DMA nodes from upstream Linux kernel P2020 dts files. Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-20powerpc: dts: p2020: Define crypto nodePali Rohár2-0/+46
Copy definition of crypto node from upstream Linux kernel P2020 dts files. Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-20powerpc: dts: p2020: Define MPIC nodesPali Rohár3-0/+124
Copy definition of MPIC nodes from upstream Linux kernel P2020 dts files. Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-20ARM: layerscape: Use ARCH_LS104?A insead of TARGET_LS104?ARDBSean Anderson1-5/+5
These frequency calculations depend on the RCW format, which is not dependent on any particular board. Switch to using ARCH symbols instead of TARGET. This whole function could probably use less ifdefs, but for now just do a minimal conversion. Fixes: 24cb6f2295 ("fsl-layerscape: Add fsl_esdhc peripheral clock support") Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-06-20arch: layerscape: Add SFP bindingSean Anderson4-0/+28
This adds an SFP binding for the processors it is present on. I have only tested this for the LS1046A. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-06-20ARM: dts: ls1021a: update the clockgen nodeSean Anderson1-52/+28
QorIQ platforms now use different clock bindings. Although we don't use the device tree for clocks on this platform, it is helpful to sync it because then the bindings will more closely match Linux. Additionally, it allows for using more clock fractions (such as platform/4). This corresponds to Linux commit b6f5e7019391 ("ARM: dts: ls1021a: update the clockgen node"). Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-06-17Merge tag 'u-boot-stm32-20220617' of ↵WIP/17Jun2022Tom Rini7-3/+615
https://source.denx.de/u-boot/custodians/u-boot-stm - Fix the stm32prog command for stm32mp platform - Add stm32mp15x DHCOR based DRC Compact board
2022-06-17Merge commit '32e0379143b433e29d76404f5f4c279067e48853' of ↵Tom Rini4-4/+54
https://github.com/tienfong/uboot_mainline
2022-06-17stm32mp1: fix reference for STMicroelectronicsPatrick Delaunay3-3/+3
Replace reference to the correct name STMicroelectronics Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17stm32mp: stpmic1: remove the debug unit request by debuggerPatrick Delaunay1-1/+0
Depending on backup register value, U-Boot SPL maintains the debug unit powered-on for debugging purpose; only BUCK1 is required for powering the debug unit, so revert the setting for all the other power lanes, except BUCK3 that has to be always on. To be functional this patch requires a modification in the debugger ,openocd for example, to update the STM32MP15 backup register when it is required to debug SPL after reset. After deeper analysis this behavior will be never supported in tools so the associated code, will be never used and the associated code can be removed. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17stm32mp: fdt: update etzpc for STM32MP13xPatrick Delaunay1-2/+151
Add support of STM32MP13x the ETZPC part of fdt.c Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Change-Id: If2777fbf66b8525a2a447056780aaa04e6b0a9a0
2022-06-17stm32mp: fdt: update etzpc for STM32MP15xPatrick Delaunay1-59/+70
Introduce STM32MP15 function and defines to prepare the STM32MP13 introduction. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Change-Id: I909b205e73dcf207e0216aae5905c3c52472020e
2022-06-17arm: dts: stm32mp: add stm32mp13 device tree for U-BootPatrick Delaunay3-0/+124
Compile the device tree of STM32MP13x boards and add the needed U-Boot add-on. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17arm: dts: socfpga: stratix10: Add freeze controller nodeDinesh Maniyam1-1/+10
The freeze controller is required for FPGA partial reconfig. This node is disable on default. Enable this node via u-boot fdt command when needed. Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com> Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-17arm: dts: socfpga: agilex: Add freeze controller nodeDinesh Maniyam1-1/+10
The freeze controller is required for FPGA partial reconfig. This node is disable on default. Enable this node via u-boot fdt command when needed. Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com> Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-17arch: arm: socfpga: timer_s10: Override udelay for secure sectionDinesh Maniyam1-1/+33
Override __udelay() as 'always inlined' function so that PSCI code run in '__secure' section can call this delay function as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-17arm: stm32mp: support 2 MAC address for STM32MP13Patrick Delaunay4-15/+52
Add support of several MAC address in OTP (3 32bits OTP word for 2 MAC address) for SOCs in STM32MP13x family: STM32MP133 and STM32MP135. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17arm: stm32mp: add support of STM32MP13xPatrick Delaunay8-2/+240
Introduce the code in mach-stm32mp and the configuration file stm32mp13_defconfig for the new STM32MP family. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17arm: stm32mp: add CONFIG_STM32MP15_PWRPatrick Delaunay2-1/+17
Add config CONFIG_STM32MP15_PWR to handle the access to regulators managed by the PWR driver defined in pwr_regulator.c This driver is only used in U-Boot by STM32MP15x family. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17arm: stm32mp: add sub config Kconfig.15xPatrick Delaunay2-118/+120
Add sub Kconfig for each SOC in the STM32 CPU family. It is a preliminary step to introduce a new SOC in the STM32MP family. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17arm: stm32mp: add choice for STM32MP SOC familyPatrick Delaunay1-10/+13
Add mandatory choice for SOC support in ARCH_STM32MP. This patch is a preliminary step for new SOC introduction in STM32MP family. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17arm: stm32mp: move code for STM32MP15xPatrick Delaunay6-324/+377
Move code and defines only needed for CONFIG_STM32MP15x in stm32mp15x.c when low level init without TFABOOT is supported. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17arm: stm32mp: move the get_otp helper function in bsecPatrick Delaunay3-17/+20
As the get_otp() helper function in bsec are common for all STM32MP family, move this function in bsec driver Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17configs: stm32mp1: move SUPPORT_SPL in STM32MP15xPatrick Delaunay2-1/+1
The SPL is only supported by STM32MP15x not by all the SOC with STM32MP arch. Only TFABOOT is supported in next products. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17ARM: dts: stm32: add STM32MP13 SoCs supportPatrick Delaunay7-0/+621
Add initial support of STM32MP13 family based on v5.18-rc2 Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17ARM: dts: stm32: Add DHCOR based DRC Compact boardMarek Vasut5-1/+494
Add DT for DH DRC Compact unit, which is a universal controller device. The system has two ethernet ports, one CAN, RS485 and RS232, USB, uSD card slot, eMMC and SDIO Wi-Fi. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17ARM: dts: stm32: Add alternate pinmux for SPI2 pinsMarek Vasut1-0/+15
Add another mux option for SPI2 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17ARM: dts: stm32: Add alternate pinmux for CAN1 pinsMarek Vasut1-0/+20
Add another mux option for CAN1 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
generated by cgit v1.1 at 2024-07-14 22:16:30 +0000