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2021-08-16ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHzMarek Vasut1-1/+1
The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM, which causes additional signal delay. At 108 MHz, this delay triggers a sporadic issue where the first bit of RX data is not received by the QSPI controller. There are two options of addressing this problem, either by using the DLYB block to compensate the extra delay, or by reducing the QSPI bus clock frequency. The former requires calibration and that is overly complex for SPL, so opt for the second option. This incurs 20ms delay during boot, when SPL loads U-Boot to DRAM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-08-16arm: dts: stm32mp15: alignment with v5.14Patrick Delaunay3-9/+42
Device tree alignment with Linux kernel v5.14-rc3 - ARM: dts: stm32: move stmmac axi config in ethernet node on stm32mp15 - ARM: dts: stm32: Configure qspi's mdma transfer to block for stm32mp151 - ARM: dts: stm32: add a new DCMI pins group on stm32mp15 - ARM: dts: stm32: fix ltdc pinctrl on microdev2.0-of7 Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-08-16stm32mp: correctly handle board_get_usable_ram_top(0)Patrick Delaunay1-0/+3
The function board_get_usable_ram_top can be called after relocation with total_size = 0 to get the uppermost pointer that is valid to access in U-Boot. When total_size = 0, the reserved memory should be not take in account with lmb library and 'gd->ram_base + gd->ram_size' can be used. It is the case today in lib/efi_loader/efi_memory.c:efi_add_known_memory() and this patch avoids that the reserved memory for OP-TEE is not part of the EFI available memory regions. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-08-16stm32mp1: stm32prog: remove stm32prog_get_tee_partitions with FIPPatrick Delaunay4-0/+10
The MTD tee partitions used to save the OP-TEE binary are needed when TF-A doesn't use the FIP container to load binaries. This patch puts under CONFIG_STM32MP15x_STM32IMAGE flag the associated code in U-Boot binary and prepare the code cleanup when CONFIG_STM32MP15x_STM32IMAGE support will be removed after TF-A migration to FIP support. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-08-16arm: stm32mp: add defconfig for trusted boot with FIPPatrick Delaunay2-2/+10
Add TF-A FIP support for trusted boot on STM32MP15x, when STM32MP15x_STM32IMAGE is not activated. With FIP support the SSBL partition is named "fip" and its size is 4MB, so the ENV partition name in device tree (for SD card or eMMC) or offset in defconfig (CONFIG_ENV_OFFSET / CONFIG_ENV_OFFSET_REDUND) need to be modified. With FIP the TEE MTD partitions are removed because the OP-TEE binray are included in the FIP containers. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-08-16arm: stm32mp: handle the OP-TEE nodes in DT with FIP supportPatrick Delaunay3-1/+16
With FIP support in TF-A (when CONFIG_STM32MP15x_STM32IMAGE is not activated), the DT nodes needed by OP-TEE are added by OP-TEE firmware in U-Boot device tree, present in FIP. These nodes are only required in trusted boot, when TF-A load the file u-boot.stm32, including the U-Boot device tree with STM32IMAGE header, in this case OP-TEE can't update the U-Boot device tree. Moreover in trusted boot mode with FIP, as the OP-TEE nodes are present in U-Boot device tree only when needed the function stm32_fdt_disable_optee can be removed. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-08-16arm: stm32mp: add config for STM32IMAGE supportPatrick Delaunay2-1/+8
By default for trusted boot with TF-A, U-Boot (u-boot-nodtb) is located in FIP container with its device tree and with the secure monitor (provided by TF-A or OP-TEE). The FIP file is loaded by TF-A BL2 and each components is extracted at the final location. This patch add CONFIG_STM32MP15x_STM32IMAGE to request the STM32 image generation for SOC STM32MP15x when FIP container is not used (u-boot.stm32 is loaded by TF-A as done previously to keep the backward compatibility). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-08-14efi_loader: add Linux magic to RISC-V crt0Heinrich Schuchardt1-2/+5
Add the Linux magic to the EFI file header to allow running our test programs with GRUB's linux command. MajorImageVersion = 1 indicates a kernel that can consume the EFI_LOAD_FILE2_PROTOCOL. This allows to dump the GRUB provided intird with our initrddump.efi tool. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-08-12Merge tag 'u-boot-rockchip-20210812' of ↵WIP/12Aug2021Tom Rini52-1203/+2216
https://source.denx.de/u-boot/custodians/u-boot-rockchip - Add Rockchip SFC driver support; - DTS sync from kernel; - emmc hs400 support for rk3399; - Fix for spinore bootdevice and MMC boot order;
2021-08-12rockchip: px30: add support for SFC for Odroid Go AdvanceChris Morgan2-0/+33
The Odroid Go Advance uses a Rockchip Serial Flash Controller with an XT25F128B SPI NOR flash chip. This adds support for both. Note that while both the controller and chip support quad mode, only two lines are connected to the chip. Changing the pinctrl to bus2 and setting tx and rx lines to 2 for this reason. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-12rockchip: px30: add the serial flash controllerChris Morgan1-0/+38
Add the serial flash controller to the devicetree for the PX30. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-12rockchip: px30: Add support for using SFCChris Morgan1-0/+64
This patch adds support for setting the correct pin configuration for the Rockchip Serial Flash Controller found on the PX30. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-12rockchip: Fix u-boot-rockchip.bin buildJohan Gunnarsson1-1/+1
Currently there are a few arm32 rockchip board configs that don't generate u-boot-rockchip.bin when running make because CONFIG_BINMAN is not enabled. This patch changes CONFIG_ARCH_ROCKCHIP to also select CONFIG_BINMAN if CONFIG_SPL and !CONFIG_ARM64. Example builds that don't generate u-boot-rockchip.bin without this patch: export ARCH=arm export CROSS_COMPILE=/usr/bin/arm-linux-gnueabihf- make kylin-rk3036_defconfig make export ARCH=arm export CROSS_COMPILE=/usr/bin/arm-linux-gnueabihf- make rock_defconfig make export ARCH=arm export CROSS_COMPILE=/usr/bin/arm-linux-gnueabihf- make tinker-rk3288_defconfig make Signed-off-by: Johan Gunnarsson <johan.gunnarsson@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-12arm: dts: sync the Rockhip 3368 SoCs from LinuxPeter Robinson5-220/+118
Sync the rk3368 DTs and associated bits from 5.14-rc1. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-12arm: dts: sync the Rockhip 3328 SoCs from LinuxPeter Robinson10-258/+487
Sync the rk3328 DTs and associated bits from 5.14-rc1. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-12arm: dts: sync the Rockhip 3399 SoCs from LinuxPeter Robinson25-447/+871
Sync the rk3399 DTs and associated bits from 5.14-rc1. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> (Remove the conflict content for vmarc-som) Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-11Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini3-8/+15
- Convert GoFlex Home Ethernet and SATA to Driver Model (Tony) - mvebu: Automatically detect CONFIG_SYS_TCLK (Pavel) - mvebu: sata_mv: Fix HDD identication during cold start (Tony) - a37xx: pci: Fix handling PIO config error responses (Pavel) - Other minor misc changes and board maintainer updates
2021-08-11Merge tag 'u-boot-amlogic-20210810' of ↵Tom Rini1-34/+0
https://source.denx.de/u-boot/custodians/u-boot-amlogic - odroid-n2: fix fdtfile suffix for n2-plus - sei610 & meson64_android cleanups to prepare android 11 boot support - use Android BCB mechanism for reboot reason instead of HW reboot flag - Switch meson64_android boot flow to use abootimg for A/B, AVB and DTBO support
2021-08-11arm64: rk3399: r4s: Remove undesirable MAC address fetching methods for ethernetXiaobo Tian1-15/+0
Remove the recommended MAC address from the network card. NanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which stores the MAC address. Signed-off-by: Xiaobo Tian <peterwillcn@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-11arm64: rk3399: r4s: Inheritance uses the sdmmc definition in dtsiXiaobo Tian1-4/+0
The host-index-min property is invalid, so it inherits from the sdmmc definition in dtsi. Signed-off-by: Xiaobo Tian <peterwillcn@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-11arm64: rk3399: r4s: correct the LEDS label nameXiaobo Tian1-3/+2
Correct the LEDS label name and remove the board type prefix, which is actually unnecessary here, removes the redefined system status LED pin. Signed-off-by: Xiaobo Tian <peterwillcn@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-11ARM: dts: rockchip: update rk3188-radxarock.dtsJohan Jonker2-53/+73
In the Linux DT the file rk3xxx.dtsi is shared between rk3066 and rk3188. Both rk3xxx.dtsi and rk3188.dtsi have recently had some updates. For a future rk3066 support in U-boot this file must also update. Move U-boot specific things in a rk3188-radxarock-u-boot.dtsi file. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-11ARM: dts: rockchip: update rk3188.dtsiJohan Jonker2-136/+356
In the Linux DT the file rk3xxx.dtsi is shared between rk3066 and rk3188. Both rk3xxx.dtsi and rk3188.dtsi have recently had some updates. For a future rk3066 support in U-boot this file must also update. Move U-boot specific things in a rk3188-u-boot.dtsi file. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-11ARM: dts: rockchip: update rk3xxx.dtsiJohan Jonker4-74/+181
In the Linux DT the file rk3xxx.dtsi is shared between rk3066 and rk3188. This file has recently had some updates. For a future rk3066 support in U-boot this file must also update. Move U-boot specific things in a rk3xxx-u-boot.dtsi file. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-11rk3399: boot_devices fix spinor node nameArtem Lapkin1-1/+1
Problem: board_spl_was_booted_from return wrong boot_devices[3] value /spi@ff1d0000 and same-as-spl dont work properly for SPINOR flash because arch/arm/mach-rockchip/spl-boot-order.c spl_node_to_boot_device need parse SPINOR flash node as UCLASS_SPI_FLASH spl-boot-order: same-as-spl > *** BOOT_SOURCE_ID 3 (2:emmc 3:spi 5:sd ... /spi@ff1d0000 > board_boot_order: could not map node @618 to a boot-device /sdhci@fe330000 > /mmc@fe320000 Solution: just change it to /spi@ff1d0000/flash@0 spl-boot-order: same-as-spl > *** BOOT_SOURCE_ID 3 (2:emmc 3:spi 5:sd ... /spi@ff1d0000/flash@0 > /sdhci@fe330000 > /mmc@fe320000 Signed-off-by: Artem Lapkin <art@khadas.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-11arm: mvebu: Hang if ddr3_init() failsPali Rohár1-1/+5
If ddr3_init() fails then DDR was not initialized and we cannot load and execute U-Boot. We cannot continue, we cannot do anything in this case, so hang. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-08-11arm: kirkwood: Do not overwrite CONFIG_SYS_TCLKPali Rohár1-2/+0
Config option CONFIG_SYS_TCLK is set by kw88f6281.h and kw88f6192.h files to correct SOC/platform value. So do not overwrite it in board config include files. Kirkwood 88F6180 and 88F6192 uses 166 MHz TCLK and Kirkwood 88F6281 uses 200 MHz TCLK. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-08-11arm: mvebu: axp: Set CONFIG_SYS_TCLK globallyPali Rohár1-3/+0
This mvebu axp platform always uses fixed 250 MHz TCLK. So specify this CONFIG_SYS_TCLK option in msys section of global file soc.h file instead of manual configuration in every board file. Now every #if-#else case of soc.h file defines CONFIG_SYS_TCLK, so remove useless default CONFIG_SYS_TCLK value from the end of soc.h file. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-08-11arm: mvebu: msys: Set CONFIG_SYS_TCLK globallyPali Rohár1-0/+2
This mvebu msys platform always uses fixed 200 MHz TCLK. So specify this CONFIG_SYS_TCLK option in msys section of global file soc.h file instead of manual configuration in every board file. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-08-11arm: mvebu: a37x: Detect CONFIG_SYS_TCLK from SAR registerPali Rohár1-0/+3
Bit 20 in SAR register specifies if TCLK is running at 200 MHz or 166 MHz. Use this information instead of manual configuration in every board file. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-08-11arm: mvebu: a38x: Detect CONFIG_SYS_TCLK from SAR registerPali Rohár1-5/+8
Bit 15 in SAR register specifies if TCLK is running at 200 MHz or 250 MHz. Use this information instead of manual configuration in every board file. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-08-09Merge tag 'u-boot-imx-20210809' of ↵WIP/09Aug2021Tom Rini69-142/+7723
https://source.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20210809 - new SOC: add support for imx8ulp - Toradex fixes for colibri (vf / imx6 / imx7 / imx8x) - convert to DM for mx28evk - Fixes for Gateworks ventana boards CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8639
2021-08-09imx: cmd: use struct cmd_tblPeng Fan2-2/+2
cmd_tbl_t is removed, need use struct cmd_tbl Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx: add i.MX8ULP EVK supportPeng Fan4-0/+273
Add i.MX8ULP EVK basic support, support SD/I2C/ENET/LPUART Log as below: I would keep some debug info for now, and after we move to be stable and production launch, we could drop that. U-Boot SPL 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) Normal Boot upower_init: soc_id=48 upower_init: version:11.11.6 upower_init: start uPower RAM service user_upwr_rdy_callb: soc=b user_upwr_rdy_callb: RAM version:12.6 Turn on switches ok Turn on memories ok Clear DDR retention ok Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F0 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. complete De-Skew PLL is locked and ready WDT: Not found! Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x3a800 by ROM_API NOTICE: BL31: v2.4(release):imx_5.10.35_2.0.0_imx8ulp_er-10-gf37e59b94 NOTICE: BL31: Built : 01:56:58, Jun 29 2021 NOTICE: upower_init: start uPower RAM service NOTICE: user_upwr_rdy_callb: soc=b NOTICE: user_upwr_rdy_callb: RAM version:12.6 U-Boot 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) CPU: Freescale i.MX8ULP rev1.0 at 744 MHz Reset cause: POR Boot mode: Single boot Model: FSL i.MX8ULP EVK DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@293a0000 Out: serial@293a0000 Err: serial@293a0000 Net: Warning: ethernet@29950000 (eth0) using random MAC address - 96:35:88:62:e0:44 eth0: ethernet@29950000 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: dts: add i.MX8ULP dtsiPeng Fan2-0/+1706
Add i.MX8ULP dtsi Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09imx8ulp: add upower api supportPeng Fan6-0/+948
Add upower api support, this is modified from upower firmware exported package. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09imx8ulp: move struct mu_type to common headerPeng Fan1-0/+25
Move struct mu_type to common header to make it reusable by upower and S400 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09imx8ulp: Add workaround for eMMC bootYe Li2-0/+17
When booting from boot part1/2, the image offset should be 0, but ROM has a bug to return 0x8000. Has to workaround the issue before ROM fix it. Use a ROM function to know boot from emmc boot part or user part So we can set the image offset accordingly. Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09imx8ulp: Use DGO_GP5 to get boot configYe Li1-1/+1
Since CMC1 MR0 only reflects high 16 bits boot cfg used for AP domian, it does not connect to low 16 bits for RTD. So we can't get the correct boot mode. Change to use DGO_GP5 of SEC_SIM which is set by ROM. Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09imx8ulp: soc: correct reset causePeng Fan1-7/+3
The CMC1 SRS reflects the current reset cause, not SSRS. Then you could get "Reset cause: WARM-WDG" when issue reset in U-Boot. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: add iomuxc supportPeng Fan2-1/+137
Add i.MX8ULP iomuxc support Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: add dummy imx_get_mac_from_fusePeng Fan1-0/+5
Add imx_get_mac_from_fuse for enet build pass Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: Allocate DCNANO and MIPI_DSI to AD domainYe Li1-0/+2
Configure DCNANO and MIPI_DSI to be controlled by AD for single boot Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: iMX8ULP: Add boot device relevant functionsYe Li2-0/+85
Read from ROM API to get current boot device. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: Probe the S400 MU device in arch initYe Li1-1/+34
Need probe the S400 MU device in arch_cpu_init_dm, so we can use S400 API in u-boot Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09imx8ulp: unify rdc functionsPeng Fan3-173/+317
Unify rdc function to rdc.c Update soc.c to use new rdc function Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: release trdc and assign lpav from RTD to APDPeng Fan1-1/+103
Rlease LPAV from RTD to APD Release gpu2D/3D to APD Set TRDC MBC2 MEM1 for iomuxc0 access Since upower depends AP/M33 SW to configure IOMUX for its PMIC i2c and MODE pins. we have to open iomuxc0 access for A35 core (domain 7) in single boot. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09arm: imx8ulp: add trdc release requestPeng Fan1-9/+17
Add TRDC release request, then we could configure resources to be accessible by A35 Domain. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: add rdc supportPeng Fan3-1/+147
There is xrdc inside i.MX8ULP, we need to configure permission to make sure AP non-secure world could access the resources. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: release and configure XRDC at early phaseYe Li3-8/+98
Since S400 will set the memory of SPL image to R/X. We can't write to any data in SPL image. 1. Set the parameters save/restore only for u-boot, not for SPL. to avoid write data. 2. Not use MU DM driver but directly call MU API to send release XRDC to S400 at early phase. 3. Configure the SPL image memory of SRAM2 to writable (R/W/X) Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
generated by cgit v1.1 at 2024-07-14 10:50:45 +0000