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2022-04-11ARM: dts: k3-j721s2: Correct timer frequencyVignesh Raghavendra1-1/+1
MCU Timer0 runs at 250MHz, and the clock-frequency defined in DT appears incorrect. Without this delays in R5 SPL are 10x off. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-04-08arm: Remove unused ep93xx codeTom Rini8-1478/+0
There are no platforms for this architecture anymore, remove unused code. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08arm: fsl-layerscape: Migrate more DP-DDR options to KconfigTom Rini1-0/+25
Based on current usage, migrate a number of DP-DDR related options to Kconfig. Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08powerpc: mpc83xx: Migrate DEFAULT_IMMR to KconfigTom Rini1-0/+4
As no platforms override this value, set it for all mpc83xx platforms. Cc: Mario Six <mario.six@gdsys.cc> Cc: Wolfgang Denk <wd@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08nds32: Migrate CONFIG_DEBUG_LED to KconfigTom Rini2-5/+0
Move this value to the board Kconfig file. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08microblaze: Migrate DCACHE/ICACHE to KconfigTom Rini1-0/+8
Move these two options to the arch Kconfig file. Cc: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2022-04-08controlcenterdc: Migrate CUSTOMER_BOARD_SUPPORT to KconfigTom Rini1-0/+4
This symbol is only possibly useful on some mvebu platforms, so move the symbol there and select it for the only current user. Cc: Mario Six <mario.six@gdsys.cc> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefan Roese <sr@denx.de>
2022-04-08spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK to KconfigTom Rini1-0/+1
This is a little tricky since SoCFPGA has code to determine this as runtime. Introduce a guard variable for platforms to select if they have a static value to use. Then for ARCH_SOCFPGA, call cm_get_qspi_controller_clk_hz() and otherwise continue the previous behavior. Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08at91: Remove unused LED codeTom Rini2-48/+0
These LED files (and CONFIG values) are unused today, remove the code in question. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08arm: integrator: Migrate platform-specific options and cleanup armcoremodule.hTom Rini1-0/+19
This converts the following to Kconfig: CONFIG_CM_INIT CONFIG_CM_REMAP CONFIG_CM_SPD_DETECT CONFIG_CM_MULTIPLE_SSRAM CONFIG_CM_TCRAM We make the first three of these options be always enabled, as that matches usage. We select the last two based on how they were defined in armcoremodule.h. This also allows us to remove some unused code in board/armltd/integrator/lowlevel_init.S Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08tegra: Migrate CI_UDC_HAS_HOSTPC to KconfigTom Rini1-0/+4
This option is only enabled for CI_UDC and !TEGRA20, so implement it as such in Kconfig directly. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Tested-by: Peter Robinson <pbrobinson@gmail.com>
2022-04-08mvebu: Move BOOTROM_ERR_REG out of CONFIG namespaceTom Rini2-2/+2
This register is referenced in one location and does not seem configurable, so remove it from CONFIG namespace. Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefan Roese <sr@denx.de>
2022-04-06riscv: alloc space exhaustedHeinrich Schuchardt1-3/+0
When trying to run qemu-riscv64_smode_defconfig with 32 harts booting fails. The debug UART shows a message alloc space exhausted 32 is the current maximum number of harts for machine virt in QEMU 7.0. Raise the default for SYS_MALLOC_F_LEN to 16 KiB. Move the setting to /Kconfig where we define SYS_MALLOC_F_LEN for other architectures too. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-04-06riscv: provide missing base extension functionsHeinrich Schuchardt2-0/+68
Provide library functions to read: * machine vendor ID * machine architecture ID * machine implementation ID Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-04-06cmd: sbi: add Performance Monitoring Unit ExtensionHeinrich Schuchardt1-0/+1
Version 1.0-rc3 of the RISC-V Supervisor Binary Interface Specification has added the Performance Monitoring Unit Extension. The sbi command should be able to detect it. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2022-04-05Merge branch '2022-04-04-platform-updates'Tom Rini12-17/+196
- Updates for exynos78x0 and TI K3 platforms
2022-04-05Merge tag 'xilinx-for-v2022.07-rc1-v2' of ↵WIP/05Apr2022Tom Rini1-0/+2
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.07-rc1 v2 xilinx: - Allow booting bigger kernels till 100MB zynqmp: - DT updates (reset IDs) - Remove unneeded low level uart initialization from psu_init* - Enable PWM features - Add support for 1EG device serial_zynq: - Change fifo behavior in DEBUG mode zynq_sdhci: - Fix BASECLK setting calculation clk_zynqmp: - Add support for showing video clock gpio: - Update slg driver to handle DT flags net: - Update ethernet_id code to support also DM_ETH_PHY - Add support for DM_ETH_PHY in gem driver - Enable dynamic mode for SGMII config in gem driver pwm: - Add driver for cadence PWM versal: - Add support for reserved memory firmware: - Handle PD enabling for SPL - Add support for IOUSLCR SGMII configurations include: - Sync phy.h with Linux - Update xilinx power domain dt binding headers
2022-04-05Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini24-80/+183
A big part is the DM pinctrl driver, which allows us to get rid of quite some custom pinmux code and make the whole port much more robust. Many thanks to Samuel for that nice contribution! There are some more or less cosmetic warnings about missing clocks right now, I will send the trivial fixes for that later. Another big chunk is the mkimage upgrade, which adds RISC-V and TOC0 (secure images) support. Both features are unused at the moment, but I have an always-secure board that will use that once the DT lands in the kernel. On top of those big things we have some smaller fixes, improving the I2C DM support, fixing some H6/H616 early clock setup and improving the eMMC boot partition support. The gitlab CI completed successfully, including the build test for all 161 sunxi boards. I also boot tested on a A64, A20, H3, H6, and F1C100 board. USB, SD card, eMMC, and Ethernet all work there (where applicable).
2022-04-05sunxi: eMMC: Improve automatic boot source detectionAndre Przywara1-0/+83
When the Allwinner BROM loads the SPL from an eMMC boot partition, it sets the boot source byte to the same value as when booting from the user data partition. This prevents us from determining the boot source to load U-Boot proper from the proper partition for sure. The generic SPL MMC code already looks at the enabled boot partition number, to load U-Boot proper from the same partition, but this fails if there is nothing bootable in this partition, as the BROM then silently falls back to the user data partition, which the SPL misses. To learn about the actual boot source anyway, we repeat the algorithm the BROM used to select the boot partition in the first place: - Test EXT_CSD[179] to check if an eMMC boot partition is enabled. - Test EXT_CSD[177] to check for valid MMC interface settings. - Check if BOOT_ACK is enabled. - Check the beginning of the first sector for a valid eGON signature. - Load the whole SPL. - Recalculate the checksum to verify the SPL is valid. If one of those steps fails, we bail out and continue loading from the user data partition. Otherwise we load from the selected boot partition. Since the boot source is needed twice in the boot process, we cache the result of this test to avoid doing this costly test multiple times. This allows the very same image file to be put onto an SD card, into the eMMC user data partition or into the eMMC boot partition, and safely loads the whole of U-Boot from there. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04arm: dts: k3-am64-ddr: Add ss_cfg reg entryDave Gerlach1-2/+3
Add 'ss_cfg' memory region for memorycontroller node which is required to enable ECC. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2022-04-04arm: dts: k3-am642-r5-evm: Mark memory with u-boot, dm-splDave Gerlach1-0/+1
Mark the memory node with u-boot,dm-spl so we can use it from early SPL. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2022-04-04ARM: dts: k3-am642: Correct timer frequencyVignesh Raghavendra2-2/+2
Timer0 runs at 200MHz,and the clock-frequency defined in DT is incorrect. Fix it. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-By: Nishanth Menon <nm@ti.com>
2022-04-04arch: arm: mach-k3: am642_init: Probe ESM nodesHari Nagalla1-4/+36
On AM64x devices, it is possible to route Main ESM0 error events to MCU ESM. MCU ESM high error output can trigger the reset logic to reset the device. So, for these devices we expect two ESM device nodes in the device tree, one for Main ESM and the another MCU ESM in the device tree. When these ESM device nodes are properly configired it is possible to route the Main RTI0 WWDT output to the MCU ESM high output through Main ESM and trigger a device reset when CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is set to '0'. On K3 AM64x devices, the R5 SPL u-boot handles the ESM device node configurations. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-04-04arm: dts: k3-am64: Add support for ESM device nodesHari Nagalla3-0/+39
Enable access to ESM0 configuration space and add Main ESM0 and MCU ESM nodes to the AM64 device tree. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-04-04spl: mmc: extend spl_mmc_boot_mode() to take mmc argumentAndre Przywara12-15/+12
Platforms can overwrite the weak definition of spl_mmc_boot_mode() to determine where to load U-Boot proper from. For most of them this is a trivial decision based on Kconfig variables, but it might be desirable the probe the actual device to answer this question. Pass the pointer to the mmc struct to that function, so implementations can make use of that. Compile-tested for all users changed. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Ley Foon Tan <ley.foon.tan@inte.com> (for SoCFPGA) Acked-by: Lokesh Vutla <lokeshvutla@ti.com> (for OMAP and K3) Reviewed-by: Simon Glass <sjg@chromium.org>
2022-04-04sunxi: clock: H6: Adjust PLL LDO before clock setupJernej Skrabec1-0/+7
BSP boot0 adjust PLL LDO regulator before clocks are initialized. Let's do that. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04sunxi: clock: H6/H616: Add resistor calibrationJernej Skrabec1-2/+7
BSP boot0 executes resistor calibration before clocks are initialized. Let's do that. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04sunxi: prcm: Add a few registersJernej Skrabec4-6/+23
H6 and H616 SPL code has a few writes to unknown PRCM registers. Now that we know what they are, let's replace magic offsets with proper register names. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04sunxi: H3: fix non working console on uart2Angelo Dureghello2-0/+5
Fix non working console on uart2, that seems releated to both Allwinner H2+ and H3. Signed-off-by: Angelo Dureghello <angelo.dureghello@timesys.com> [Andre: remove H2+, rearrange pin setup order] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04Add ethernet0 alias in Nanopi NEO's device treeBaltazár Radics1-0/+4
This syncs the sun8i-h3-nanopi-neo.dts from the Linux tree, from tag v5.18-rc1. The alias is required to enable automatic MAC address generation. Signed-off-by: Baltazár Radics <baltazar.radics@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04sunxi: Support building a SPL as a TOC0 imageSamuel Holland1-0/+2
Now that mkimage can generate TOC0 images, and the SPL can interpret them, hook up the build infrastructure so the user can choose which image type to build. Since the absolute load address is stored in the TOC0 header, that information must be passed to mkimage. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04sunxi: Support SPL in both eGON and TOC0 imagesSamuel Holland3-13/+33
SPL uses the image header to detect the boot device and to find the offset of the next U-Boot stage. Since this information is stored differently in the eGON and TOC0 image headers, add code to find the correct value based on the image type currently in use. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04pwm: sunxi: Remove non-DM pin setupSamuel Holland1-1/+0
This is now handled automatically by the pinctrl driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04sunxi: Remove options and setup code for I2C2-I2C4Samuel Holland3-40/+1
These options are not currently enabled anywhere. Any new users should use DM clocks and pinctrl. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04sunxi: Remove non-DM GMAC pin setupSamuel Holland1-2/+0
This is now handled automatically by the pinctrl driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04net: sunxi_emac: Remove non-DM pin setupSamuel Holland1-1/+0
This is now handled automatically by the pinctrl driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04sunxi: pinctrl: Create the driver skeletonSamuel Holland2-0/+6
Create a do-nothing driver for each sunxi pin controller variant. Since only one driver can automatically bind to a DT node, since the GPIO driver already requires a manual binding process, and since the pinctrl driver needs access to some of the same information, refactor the GPIO driver to be bound by the pinctrl driver. This commit should cause no functional change. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04board: starqltechn: get board usable - add bootcmd and docsDzmitry Sankouski3-9/+19
U-boot is intended to replace linux kernel in android boot image(ABL), and it's FIT payload to replace initramfs file. The boot process is similar to boot image with linux: - android bootloader (ABL) unpacks android boot image - ABL sets `linux,initrd-start property` in chosen node in unpacked FDT - ABL sets x0 register to FDT address, and passes control to u-boot - u-boot reads x0 register, and stores it in `prevbl_fdt_addr` env variable - u-boot reads `linux,initrd-start` property, and stores it in `prevbl_initrd_start_addr` In this way, u-boot bootcmd relies on `prevbl_initrd_start_addr` env variable, and boils down to `bootm $prevbl_initrd_start_addr`. If more control on boot process is desired, pack a boot script in FIT image, and put it to default configuration What done: - strip unneeded config options - add FIT image support - add framebuffer node, u-boot logo and video console - increase LMB_MAX_REGIONS, to store all linux dtb reserved memory regions - add linux kernel image header Uart driver causes hang, when u-boot is used in android boot image instead of linux. Temporary disable console driver, until investigated and fixed. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Ramon Fried <rfried.dev@gmail.com>
2022-04-04arm: init: save previous bootloader dataDzmitry Sankouski2-0/+96
When u-boot is used as a chain-loaded bootloader (replacing OS kernel), previous bootloader leaves data in RAM, that can be reused. For example, on recent arm linux system, when chainloading u-boot, there are initramfs and fdt in RAM prepared for OS booting. Initramfs may be modified to store u-boot's payload, thus providing the ability to use chainloaded u-boot to boot OS without any storage support. Two config options added: - SAVE_PREV_BL_INITRAMFS_START_ADDR saves initramfs start address to 'prevbl_initrd_start_addr' environment variable - SAVE_PREV_BL_FDT_ADDR saves fdt address to 'prevbl_fdt_addr' environment variable Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Tom Rini <trini@konsulko.com>
2022-04-04Merge branch 'next'Tom Rini130-2918/+4068
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-04Merge tag 'u-boot-at91-2022.07-a' of ↵WIP/04Apr2022-nextTom Rini9-445/+1649
https://source.denx.de/u-boot/custodians/u-boot-at91 into next First set of u-boot-at91 features for the 2022.07 cycle: This feature set includes the new driver for the Atmel TCB timer, alignment in DT for sama7g5 and sama7g5ek board, one Kconfig conversion for external reset, and the usage of Galois tables from ROM for sama5d2 device.
2022-04-01arm64: ls1046a: Support semihosting fallbackSean Anderson1-1/+2
Use the semihosting_enabled function to determine whether or not to enable semihosting devices. This allows for graceful fallback in the event a debugger is not attached. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01arm64: Catch non-emulated semihosting callsSean Anderson1-0/+47
If a debugger is not attached to U-Boot, semihosting calls will raise a synchronous abort exception. Try to catch this and disable semihosting so we can e.g. use another uart if one is available. In the immediate case, we return an error, since it is not always possible to check for semihosting beforehand (debug uart, user-initiated load command, etc.) We handle all possible semihosting instructions, which is probably overkill. However, we do need to keep track of what instruction set we're using so that we don't suppress an actual error. A future enhancement could try to determine semihosting capability by inspecting the processor state. There's an example of this at [1] for RISC-V. The equivalent for ARM would inspect the monitor modei enable/select bits of the DSCR. However, as the article notes, an exception handler is still helpful in order to catch disconnected debuggers. [1] https://tomverbeure.github.io/2021/12/30/Semihosting-on-RISCV.html#avoiding-hangs-when-a-debugger-is-not-connected Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01arm: smh: Add option to detect semihostingSean Anderson2-0/+42
These functions are intended to support detecting semihosting and falling back gracefully to alternative implementations. The test starts by making semihosting call. SYS_ERRNO is chosen because it should not mutate any state. If this semihosting call results in an exception (rather than being caught by the debugger), then the exception handler should call disable_semihosting() and resume execution after the call. Ideally, this would just be part of semihosting by default, and not a separate config. However, to reduce space ARM SPL doesn't include exception vectors by default. This means we can't detect if a semihosting call failed unless we enable them. To avoid forcing them to be enabled, we use a separate config option. It might also be possible to try and detect whether a debugger has enabled (by reading HDE from DSCR), but I wasn't able to figure out a way to do this from all ELs. This patch just introduces the generic code to handle detection. The next patch will implement it for arm64 (but not arm32). Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01arm64: Import some ESR and SPSR defines from LinuxSean Anderson2-0/+416
This imports some defines for esr and spsr from Linux v5.16. I have modified the includes and fixed some indentation nits but otherwise it is the same. There are a lot more defines than we need, but it doesn't hurt. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01arm64: Save spsr in pt_regsSean Anderson2-2/+5
This register holds "pstate" which includes (among other things) the instruction mode the CPU was in when the exception was taken. This is necessary to correctly interpret instructions at elr. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01arm64: Save esr in pt_regsSean Anderson5-26/+26
To avoid passing around an extra register everywhere, save esr in pt_regs like the rest. For proper alignment we need to have a second (unused) register. All the printfs have to be adjusted, since it's now an unsigned long and not an int. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01ls1046ardb: Add support for JTAG bootSean Anderson1-0/+2
This adds support for booting entirely from JTAG while using a hard-coded RCW. With these steps, it is not necessary to program a "good" RCW using CodeWarrior. The method here can be performed with any JTAG adapter supported by OpenOCD, including the on-board CMSIS-DAP (albeit very slowly). These steps require LS1046A support in OpenOCD, which was added in [1]. [1] https://sourceforge.net/p/openocd/code/ci/5b70c1f679755677c925b4e6dd2c3d8be4715717/ Signed-off-by: Sean Anderson <sean.anderson@seco.com> [trini: Add reference to doc/board/nxp/ls1046ardb.rst]
2022-04-01arm: smh: Add some functions for working with the host consoleSean Anderson1-0/+18
This adds three wrappers around the semihosting commands for reading and writing to the host console. We use the more standard getc/putc/puts names instead of readc/writec/write0 for familiarity. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01arm: smh: Remove smhload commandSean Anderson1-76/+0
This command's functionality is now completely implemented by the standard fs load command. Convert the vexpress64 boot command (which is the only user) and remove the implementation. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
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