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2021-07-07Merge tag 'dm-pull-6jul21' of https://source.denx.de/u-boot/custodians/u-boot-dmWIP/07Jul2021Tom Rini4-10/+40
various minor sandbox improvements
2021-07-07Merge branch '2021-07-06-update-to-gcc11-clang11'Tom Rini2-0/+4
- Update CI to use gcc-11.1 and clang-11 to build everything. This requires a few fixes to the code that these newer compilers have exposed.
2021-07-07Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini1-2/+2
2021-07-07x86: Drop _X86EMU_env definition when CONFIG_BIOSEMU is usedBin Meng1-0/+2
With x86 we can execute an option ROM either natively or using the x86 emulator (if enabled with CONFIG_BIOSEMU). Both of these share the _X86EMU_env variable, with the native code using it to hold register state during interrupt processing. At present, in 32-bit U-Boot, the variable is declared twice, once in common code and once in code only compiled with CONFIG_BIOSEMU. With GCC 11 this causes a 'multiple definitions' error on boards with CONFIG_BIOSEMU. Drop the emulator definition when CONFIG_BIOSEMU is used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-07bootstage: Eliminate when not enabledTom Rini1-0/+2
When we do not have bootstage enabled, rather than include an empty dummy function, we just don't reference it. This saves us space in some tight builds. This also shows a few cases where show_boot_progress was incorrectly guarded before. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07Merge tag 'u-boot-atmel-fixes-2021.10-a' of ↵Tom Rini7-7/+10
https://source.denx.de/u-boot/custodians/u-boot-atmel First set of u-boot-atmel fixes for 2021.10 cycle: This small fixes set is dedicated to fixing the onewire subsystem for the at91 boards which was broken since 2020.04.
2021-07-07riscv: dts: add OpenPiton RISC-V board dts supportTianrui Wei1-2/+2
Previous device tree for OpenPiton emits a warning during compilation. This commit fixes the previous warning adds dts to the OpenPiton RISC-V board and added the device tree to MAINTAINER file. Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com> Reported-by: Tom Rini <trini@konsulko.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06Merge branch '2021-07-06-platform-updates'Tom Rini19-31/+1793
- mpc8379erdb DM_USB, DM_PCI and DM_ETH support. - Drop PCI support from the integrator family of boards - Add synquacer support - Assorted lpc32xx updates and improvements - snapdragon (and related) fixes, Broadcom iproc update
2021-07-06arm: dts: db410c: Add missing cd-gpios for SD card detectionStephan Gerhold1-1/+3
It looks like SD card detection is broken at the moment for DB410c. The eMMC is detected correctly, but the SD card is not. This is probably similar to the issue fixed in commit 850514740358 ("mmc: msm_sdhci: Use mmc_of_parse for setting host_caps") for eMMC, except that the SD card does not have a property like "non-removable" that skips the card detection. The SDHCI on DB410c cannot detect itself if a SD card is inserted, so add the necessary cd-gpios to make SD card detection work again. While at it, fix the #gpio-cells for the soc_gpios to avoid DTC warnings - the soc_gpios are actually already used with two cells for the gpio-leds so this was just wrong all the time. Cc: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06arm: snapdragon: Fix typo in clk_bcr_update()Sheep Sun1-5/+5
Fix typo in clock-snapdragon.c Signed-off-by: Sheep Sun <sunxiaoyang2003@gmail.com>
2021-07-06arm: snapdragon: Use correct GICC register on APQ8016Sheep Sun1-1/+1
The GICC register used by u-boot is 0x0a20c000, which is actually a GICC for WCNSS, the WLAN processor. U-boot runs on the Application Processor, therefore it should use APCS GICC instead. Hence, correct it with APCS GICC register address. Signed-off-by: Sheep Sun <sunxiaoyang2003@gmail.com>
2021-07-06arm: lpc32xx: add EA LPC3250 DevKitv2 board supportTrevor Woerner3-0/+21
Add basic support for running U-Boot on the Embedded Artists LPC3250 Developer's Kit v2 board by launching U-Boot from the board's s1l loader (which comes pre-installed on the board). Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2021-07-06lpc32xx: import device tree from LinuxTrevor Woerner2-0/+781
Import the dtsi, dts, and clock binding files for the lpc32xx ea3250 board directly and unmodified from the latest Linux kernel. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2021-07-06lpc32xx: Kconfig: switch to CONFIG_CONS_INDEXTrevor Woerner2-4/+3
There's nothing special or unique to the lpc32xx that requires its own config parameter for specifying the console uart index. Therefore instead of using the lpc32xx-specific CONFIG_SYS_LPC32XX_UART include parameter, use the already-available CONFIG_CONS_INDEX from Kconfig. Signed-off-by: Trevor Woerner <twoerner@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-06board: synquacer: Add DeveloperBox 96boards EE supportMasami Hiramatsu1-0/+14
Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-06ARM: dts: synquacer: Add device trees for DeveloperBoxMasami Hiramatsu5-0/+800
Add device trees for 96boards EE DeveloperBox and basement SynQuacer SoC dtsi. These files are imported from EDK2 commit 83d38b0b4c0f240d4488c600bbe87cea391f3922 as-is (except for the changes #include path and some macros). And add U-Boot specific changes in synquacer-sc2a11-developerbox-u-boot.dtsi Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-06gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefsMasami Hiramatsu2-7/+95
Since some SoCs and boards do not hae extra asm/arch/gpio.h, introduce CONFIG_GPIO_EXTRA_HEADER instead of adding !define(CONFIG_ARCH_XXXX) in asm/gpio.h. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-06arm: iproc: Add higher speed configurationsChris Packham1-13/+16
Add support for 1.3GHz, 1.35GHz and 1.4GHz parts. This is based on equivalent code in Broadcom's LDK 5.0.6. Signed-off-by: Chris Packham <judge.packham@gmail.com>
2021-07-06mpc8379erdb: enable DM_USB DM_PCI DM_ETHSinan Akman2-0/+54
Signed-off-by: Sinan Akman <sinan@writeme.com>
2021-07-06sandbox: cros-ec: Add tests for the Chromium OS EC PWM driverAlper Nebi Yasak2-0/+16
This patch adds a limited pulse-width modulator to sandbox's Chromium OS Embedded Controller emulation. The emulated PWM device supports multiple channels but can only set a duty cycle for each, as the actual EC doesn't expose any functionality or information other than that. Though the EC supports specifying the PWM channel by its type (e.g. display backlight, keyboard backlight), this is not implemented in the emulation as nothing in U-Boot uses this type specification. This emulated PWM device is then used to test the Chromium OS PWM driver in sandbox. Adding the required device node to the sandbox test device-tree unfortunately makes it the first PWM device, so this also touches some other tests to make sure they still use the sandbox PWM. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-06sandbox: fix sandbox_reset()Heinrich Schuchardt1-3/+0
state_uninit() and dm_uninit() are mutually exclusive: state_uninit() prints via drivers. So it cannot be executed after dm_uninit(). dm_uninit() requires memory. So it cannot be executed after state_uninit() which releases all memory. Just skip dm_uninit() when resetting the sandbox. We will wake up in a new process and allocate new memory. So this cleanup is not required. We don't do it in sandbox_exit() either. This avoids a segmentation error when efi_reset_system_boottime() is invoked by a UEFI application. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-06sandbox: ensure that state->ram_buf is in low memoryHeinrich Schuchardt1-4/+8
Addresses in state->ram_buf must be in the low 4 GiB of the address space. Otherwise we cannot correctly fill SMBIOS tables. This shows up in warnings like: WARNING: SMBIOS table_address overflow 7f752735e020 Ensure that state->ram_buf is initialized by the first invocation of os_malloc(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-06sandbox: Support signal handling only when requestedSimon Glass2-3/+16
At present if sandbox crashes it prints a message and tries to exit. But with the recently introduced signal handler, it often seems to get stuck in a loop until the stack overflows: Segmentation violation Segmentation violation Segmentation violation Segmentation violation Segmentation violation Segmentation violation Segmentation violation ... The signal handler is only useful for a few tests, as I understand it. Make it optional. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-06Merge https://source.denx.de/u-boot/custodians/u-boot-riscvWIP/06Jul2021-v2Tom Rini9-1/+1681
2021-07-06riscv: dts: add dts for unmatched rev1Zong Li4-1/+1501
The difference between unmatched rev3 and rev1 is DDR timing, the rev3 uses 1866 MT/s for 16GiB, and rev1 uses 2133 MT/s for 8GiB. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06board: sifive: Add an interface to get PCB revisionZong Li1-0/+15
There are different DDR parameter settings for different board revisions. Add a new interface to get the PCB revision to determine which DT should be selected at runtime. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06riscv: sifive: fu740: Support i2c in splZong Li2-0/+5
Enable SPL_I2C_SUPPORT for fu740, and add 'u-boot,dm-spl' property in i2c node. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controllerZong Li1-0/+2
Enable the Opencores I2C controller on FU740 Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06ARM: dts: at91: fix the GPIO polarity for onewireEugen Hristev7-7/+10
The GPIO polarity for onewire must be GPIO_ACTIVE_HIGH. On previous versions this used to work as it looks like the right flag values are being passed since : https://lists.denx.de/pipermail/u-boot/2020-April/407195.html And that series broke the old functionality for onewire nodes. Some boards had the correct value for the polarity, but it wasn't clear so I replaced it with the right macro for the flag, instead of an empty value. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-07-06board: riscv: add openpiton-riscv64 SoC supportTianrui Wei3-0/+158
This patch adds openpiton-riscv64 SOC support. In particular, this board supports a standard bootflow through zsbl->u-boot SPL-> opensbi->u-boot proper->Linux. There are separate defconfigs for building u-boot SPL and u-boot proper Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com> Signed-off-by: Jonathan Balkind <jbalkind@ucsb.edu> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06board: sl28: add DSA support for variant 2Michael Walle2-0/+47
Now that u-boot gained DSA support, and it is already enabled for the kontron_sl28 board, add the last missing piece and enable the corresponding devices it in the device tree. Signed-off-by: Michael Walle <michael@walle.cc>
2021-07-06arm: dts: ls1028a: disable enetc-2 by defaultVladimir Oltean1-1/+1
The enetc-2 port is used as DSA master (connected back-to-back to mscc_felix_port4). Since the convention is to not enable ports in the common SoC dtsi unless they are used on the board, then enable enetc-2 only when mscc_felix_port4 itself is enabled. All existing device trees appear to adhere to this rule, so disable enetc-2 in the SoC dtsi. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06arm: dts: ls1028a: declare the fixed-link speeds for the internal ENETC portsVladimir Oltean1-0/+10
To comply with the device tree bindings expectations for an Ethernet controller, as well as to simplify the driver code, declare fixed-link nodes for the internal ENETC ports (attached to the mscc_felix switch). Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06arm: dts: ls1028a: enable internal RGMII delays for the LS1028A-QDS AR8035 PHYVladimir Oltean1-1/+1
There are no PCB trace delays on this board, so the PHY needs to enable its internal ones in order to have a proper electrical connection to the enetc MAC. Fixes: b32e9a757837 ("arm: dts: ls1028a updates for network interfaces") Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06arm: dts: ls1028a: enable the switch CPU port for the LS1028A-QDSVladimir Oltean8-0/+72
Due to an upstream change, the ls1028a.dtsi bindings for the mscc_felix switch got accepted with all ports disabled by default and with no link to the DSA master - this needs to be done on a per board basis. Note that enetc-2 is not currently disabled in the ls1028a.dtsi, but presumably at some point it might become. Explicitly enable it in the QDS device trees anyway, to proactively avoid issues when that happens. Fixes: a7fdac7e2a2a ("arm: dts: ls1028a: define QDS networking protocol combinations") Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-01Merge tag 'xilinx-for-v2021.10' of ↵WIP/01Jul2021-nextTom Rini47-859/+1065
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.10 clk: - Add driver for Xilinx Clocking Wizard IP fdt: - Also record architecture in /fit-images net: - Fix plat/priv data handling in axi emac - Add support for 10G/25G speeds pca953x: - Add missing dependency on i2c serial: - Fix dependencies for DEBUG uart for pl010/pl011 - Add setconfig option for cadence serial driver watchdog: - Add cadence wdt expire now function zynq: - Update DT bindings to reflect the latest state and descriptions zynqmp: - Update DT bindings to reflect the latest state and descriptions - SPL: Add support for ECC DRAM initialization - Fix R5 core 1 handling logic - Enable firmware driver for mini configurations - Enable secure boot, regulators, wdt - Add support xck devices and 67dr - Add psu init for sm/smk-k26 SOMs - Add handling for MMC seq number via mmc_get_env_dev() - Handle reserved memory locations - Add support for u-boot.itb generation for secure OS - Handle BL32 handoffs for secure OS - Add support for 64bit addresses for u-boot.its generation - Change eeprom handling via nvmem aliases
2021-06-28Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-sh ↵WIP/28Jun2021-nextTom Rini11-1/+1308
into next - V3U Falcon board support
2021-06-28Merge tag 'v2021.07-rc5' into nextTom Rini69-97/+2149
Prepare v2021.07-rc5 # gpg: Signature made Mon 28 Jun 2021 03:39:36 PM EDT # gpg: using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C # gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate] # Conflicts: # configs/am64x_evm_r5_defconfig
2021-06-28arm64: Fix relocation of env_addr if POSITION_INDEPENDENT=yKunihiko Hayashi1-0/+5
If both POSITION_INDEPENDENT and SYS_RELOC_GD_ENV_ADDR are enabled, wherever original env is placed anywhere, it should be relocated to the right address. Relocation offset gd->reloc_off is calculated with SYS_TEXT_BASE in setup_reloc() and env address gd->env_addr is relocated by the offset in initr_reloc_global_data(). gd->env_addr = (orig env) + gd->reloc_off = (orig env) + (gd->relocaddr - SYS_TEXT_BASE) However, SYS_TEXT_BASE isn't always runtime base address when POSITION_INDEPENDENT is enabled. So the relocated env_addr might point to wrong address. For example, if SYS_TEXT_BASE is zero, gd->env_addr is out of memory location and memory exception will occur. There is a difference between linked address such as SYS_TEXT_BASE and runtime base address. In _main, the difference is calculated as "run-vs-link" offset. The env_addr should also be added to the offset to fix the address. gd->env_addr = (orig env) + ("run-vs-link" offset) + gd->reloc_off = (orig env) + (SYS_TEXT_BASE - _start) + (gd->relocaddr - SYS_TEXT_BASE) = (orig env) + (gd->relocaddr - _start) Cc: Marek Vasut <marex@denx.de> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de>
2021-06-28arm64: dts: zynqmp: Add psgtr and phy entry for USB and SATA nodePiyush Mehta1-0/+26
This patch adds psgtr clocks and phy entry for USB0, USB1 and SATA node for zc1751-xm017-dc3 board. Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-25Merge tag 'u-boot-imx-20210625' of ↵Tom Rini1-12/+6
https://gitlab.denx.de/u-boot/custodians/u-boot-imx Fixes for 2021.07 ----------------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/7903
2021-06-24ARM: rmobile: beacon: Set CONFIG_RZ_G2 on Beacon boardsAdam Ford1-0/+3
The board detection is incorrectly stating it's an rcar3 variant instead of an RZ/G2 variant on all the r8a774*1_beacon boards. Set the flag to correctly display as RZ/G2[M/N/H] Signed-off-by: Adam Ford <aford173@gmail.com>
2021-06-24ARM: rmobile: Add basic PSCI support for R8A779A0 V3U FalconHai Pham2-0/+53
Enable basic PSCI support for R8A779A0 V3U Falcon Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-06-24ARM: renesas: Add R8A779A0 V3U Falcon board codeHai Pham3-1/+41
Add board code for the R8A779A0 V3U Falcon board. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> -- Marek: - various small rebase fixes and clean ups
2021-06-24ARM: renesas: Add R8A779A0 V3U platform codeHai Pham3-0/+7
Add platform code to support R8A779A0 V3U SoC. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-06-24ARM: dts: renesas: Add RPC node to R8A779A0 V3UMarek Vasut1-0/+13
The R-Car V3U does support RPC interface, however the support for it is missing in upstream Linux DTs as of commit 9f4ad9e425a1 ("Linux 5.12"), add the node into u-boot.dtsi to let U-Boot access the SPI NOR or HF. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-06-24ARM: dts: renesas: Add R8A779A0 V3U DT extrasHai Pham1-0/+12
Add R8A779A0 V3U DT extras for U-Boot. Based on "ARM: dts: renesas: Add R8A779A0 V3U DTs" by Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-06-24ARM: dts: renesas: Add R8A779A0 V3U Falcon DTsMarek Vasut2-0/+212
Import R8A779A0 V3U Falcon DTs from Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-06-24ARM: dts: renesas: Add R8A779A0 V3U DTs and headersMarek Vasut1-0/+970
Import R8A779A0 V3U DTs and headers from Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-06-23Merge https://source.denx.de/u-boot/custodians/u-boot-x86WIP/23Jun2021Tom Rini3-0/+3
- x86: Discard .note.gnu.property sections - nvme: Skip block device creation for inactive namespaces - nvme: Convert NVMe doc to reST, and various minor fixes
generated by cgit v1.1 at 2024-10-12 03:09:06 +0000